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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 16/155頁(yè) |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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8-8
M32000D3FP User's Manual
POWER MANAGEMENT FUNCTION
8.3 CPU sleep mode
Clock supply to the M32R CPU stops in CPU sleep mode. In this mode, the internal DRAM, cache memory,
memory controller and external bus interface continue to operate and the internal DRAM can be accessed
from the external bus.
8.3.1 Switching to CPU sleep mode
To switch to CPU sleep mode, set the PM0 and PM1 bits in the MPMR to "10". When CPU sleep mode
is set, clock supply to the CPU stops after 1 internal clock.
8.3.2 Bus state in CPU sleep mode
In CPU sleep mode, the M32R CPU stops operating, however, the BIU and memory controller continue
__________
operating. Bus hold control using HREQ and HACK and the internal DRAM access from an external bus
master (the slave M32000D3FP is on hold) function as per normal operations.
Bus control signals not in the hold state go to the idle state because the CPU does not access anything.
However, a write cycle may be carried out immediately before switching to CPU sleep mode, if an instruction
writing to an external address was being executed prior to switching.
Table 8.3.1 Pin conditions in CPU sleep mode
pin name
idle condition
hold condition
A8 - A30, SID, ST
output undefined
high-impedance
____
__
___
______
BCH, BCL, R/W, BS, BURST
output "H"
high-impedance
D0 - D15
high-impedance
high-impedance (other than note 1)
__
DC
high-impedance
high-impedance (other than note 2)
_____
HACK
output "H"
output "L"
_____
STBY
output "H"
other pins
retain condition immediately before
entering CPU sleep mode
___
__
Notes 1: Output when internal DRAM is read by an external bus master (CS="L", R/W="H")
___
2: Output when internal DRAM is accessed by an external bus master (CS = "L")
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