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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 133/155頁(yè) |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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M32000D3FP User's Manual
INTERNAL MEMORY AND MEMORY CONTROLLER
5-13
D
bit name
function
R
W
24 - 29
Not assigned.
0
x
30, 31
PM0, PM1
00: normal operation mode
(low power consumption
01: (reserved)
mode)
10: CPU sleep mode
11: standby mode
5.5 Memory controller
D24
25
26
27
28
29
30
D31
PM1
PM0
(2) Power management control register (MPMR) <address: H'FFFF FFFB>
<at reset: H'00>
The power management control register (MPMR) controls the low power consumption mode of the
M32000D3FP. The CPU sleep mode and standby mode are selected by the PM0 and PM1 (power
management) bits (For details, refer to Chapter 8 "Power management function".).
CPU sleep mode (PM0, PM1 = "10")
When the PM0 and PM1 bits are set to "10", the M32000D3FP switches to CPU sleep mode. Clock
supply to the M32R CPU stops in CPU sleep mode.
______
_______
When an INT, SBI or RST signal is input to the M32000D3FP, the state returns to normal operation
mode.
______
If the M32000D3FP is returned to normal operation following an INT or an SBI signal input then
the contents of MPMR are retained. After using these as an input factor recognition flag for the
external interrupt handler or the SBI handler, PM0 and PM1 should be cleared to "00". The
contents of the MPMR are retained until they are cleared by the external interrupt handler, however,
the M32000D3FP will not switch to CPU sleep mode again until PM0 and PM1 are once more set
to "10".
It is not guaranteed that the device will switch to standby mode or CPU sleep mode again without
first clearing PM0 and PM1 to "00" on return from CPU sleep mode. Please ensure this operation
is implemented.
standby mode (PM0, PM1 = "11")
When the PM0 and PM1 bits are set to "11", the M32000D3FP switches to standby mode. All
clock supplies stop, however, the contents of the internal DRAM are retained by self-refresh when
the M32000D3FP is in standby mode.
__________
_______
When a WKUP or RST signal is input to the M32000D3FP, the state returns to normal operation
mode.
__________
If the M32000D3FP is returned to normal operation following a WKUP signal input then the contents
of MPMR are retained. After using this as an input factor recognition flag for the reset interrupt
handler, PM0 and PM1 should be cleared to "00". The contents of the MPMR are retained until
they are cleared by the reset interrupt handler, however, the M32000D3FP will not switch to CPU
sleep mode again until PM0 and PM1 are once more set to "11".
It is not guaranteed that the device will switch to standby mode or CPU sleep mode again without
first clearing PM0 and PM1 to "00" on return from standby mode. Please ensure this operation is
implemented.
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