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| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 135/155頁 |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
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5-14
M32000D3FP User's Manual
INTERNAL MEMORY AND MEMORY CONTROLLER
D
bit name
function
R
W
24
CP
0: no purge
0
(cache purge)
1: purge
25 - 29
Not assigned.
0
x
30, 31
CM0, CM1
00: cache mode is not changed
(cache mode)
01: cache-off mode
10: internal instruction/data cache mode
11: instruction cache mode
5.5 Memory controller
(3) Cache control register (MCCR) <address: H'FFFF FFFF>
D24
25
26
27
28
29
30
D31
CM1
CM0
CP
The cache control register (MCCR) controls the internal cache memory. Cache operation mode is
controlled by the CM0 and CM1 (cache memory) bits. The cache can be purged by writing "1" to the
CP (cache purge) bit.
cache-off mode (CM0, CM1 = "01")
In this mode, the cache memory is off and no bus accesses does not pass through the cache. This
mode is automatically set immediately after reset.
internal instruction/data cache mode (CM0, CM1 = "10")
In this mode, the cache memory functions as a cache for both the instructions and data from the
internal DRAM, and caches all bus accesses to the DRAM. Caching is by the direct map method.
Writing is by the copy back method.
instruction cache mode (CM0, CM1 = "11")
In this mode, the cache memory functions as an instruction cache for the internal DRAM and the
external memory, and caching is applied to instruction fetch accesses. When instruction codes in
the user space are overwritten, instruction code coherency in cache memory is not guaranteed.
To purge the cache without the changing cache mode, write "1" to the CP bit and "00" to the CM0
and CM1 bits. In this case, the value written to the CM0 and CM1 are ignored and the value written
immediately before is retained, however, when the CM0 and CM1 are read, the values of the current
cache mode will be read.
When changing the cache mode, purge the cache in advance. Cache purge is not performed automatically.
The consistency between data on the cache memory and data on the internal DRAM is kept through the
purging operation.
Purging the cache in instruction cache mode nullifies all data in the cache memory. Purging the cache in
internal instruction/data cache mode reconstitutes the updated data in the cache to the internal DRAM,
then nullifies all data.
<at reset: H'01>
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