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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 150/155頁(yè) |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
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6-14
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6.6 External bus master access
_____
After the M32000D3FP switches to the hold state and an "L" level is input to CS, the internal DRAM can
be accessed from the system bus.
6.6.1 External bus master read cycle
__________
_____
When the M32000D3FP is in the hold state (HACK = "L") and an "L" level is input to CS, the M32000D3FP
___
interprets it as a bus access request to the internal DRAM. In this case, when the R/W signal is an "H"
level, the memory controller drives a read cycle to the internal DRAM. In the read cycle, the 16-bit data
_______
for the address specified with A8 to A30, is output from D0 to D15 regardless of the BCH and BCL settings.
_____
Also the DC signal is output.
The M32000D3FP reads 128 bits of data from the block on the 128-bit boundary including the requested
address into the 128-bit buffer of the bus interface unit. 3 to 7 CLKIN clock periods are necessary for the
first bus access, however, when reading consecutive address within the 128-bit boundary, the subsequent
read bus cycles are completed in 1 CLKIN clock period because a read from the internal DRAM does not
take place.
Once the external bus master read cycle has been driven, it cannot be aborted. When an "L" level is input
_____
to CS and an access has started, the values of this and other control signals should be held during the
_____
wait cycles (that is while DC = "H"). After DC outputs an "L" level (access complete), return CS to the "H"
level between the CLKIN falling edge corresponding to the last read cycle and the following CLKIN falling
_____
edge. Return HREQ to the "H" level to return the M32000D3FP from the hold state to normal operation
_____
mode either at the same time as or after CS is returned to the "H" level.
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