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參數資料
| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數： | 65/155頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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M32000D3AFP User's Manual
OVERVIEW
1-9
1.3 Pin function
Table 1.3.1 Pin function (2/3)
type
pin name
name
I/O
function
bus
SID
space
Output Space identifier between user space and I/O space.
control
identifier
(Hi-z)*
SID = "L": user space
SID = "H": I/O space
SID is bidirectional. When accessing the internal DRAM
from outside the M32000D3FP while the M32000D3FP
is in the hold state, input an "L" level from the system
bus side.
____
BCH, BCL
byte control
I/O
Indicates the valid byte positions of transferred data.
(Hi-z)*
____
BCH corresponds to the MSB side (D0 to D7), and
____
BCL corresponds to the LSB side (D8 to D15). During
____
a read bus cycle, both BCH and BCL are an "L" level.
____
During a write bus cycle, either BCH and/or BCL is
an "L" level depending on the byte(s) to be written.
When accessing the internal DRAM from an external
bus master, the byte control signal is input from the
system bus side.
___
BS
bus start
output
When the M32000D3FP drives an external bus cycle,
(Hi-z)*
___
BS goes to an "L" level at the start of the bus cycle.
___
In burst transfer, BS goes to "L" level for each transfer
cycle. When accessing internal resources such as an
___
internal DRAM or an internal I/O register, BS is not
output.
ST
bus status
output
Indicates whether the bus cycle that the M32000D3FP
(Hi-z)*
drives is an instruction fetch access cycle or an operand
access cycle.
ST = "L": for instruction fetch access
ST = "H": for operand access
ST = undefined: when idle
__
R/W
read/write
I/O
__
Outputs R/W to identify whether the external bus cycle
(Hi-z)*
a read or a write cycle. When accessing the internal
__
DRAM from an external bus master, R/W is input from
the external bus.
______
BURST
burst
output
The M32000D3FP drives two consecutive bus cycles
(Hi-z)*
to access 32-bit data allocated on the 32-bit word
boundary.
For instruction fetches, it drives 8 (max.) consecutive
cycles (8 cycles in instruction cache mode) to data
on the 128-bit boundary. During these consecutive
______
bus cycles, BURST goes to "L" level. When accessing
32-bit data, an "L" level followed by an "H" level is
output from address A30, because the MSB-side
16 bits are accessed prior to the LSB-side 16 bits.
When accessing 128-bit data, the addresses are
output from an arbitrary 16-bit aligned address and
wraparound within 128-bit aligned boundary.
* (Hi-z): This pin goes to high-impedance in the hold state.
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