- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98004 > M32000D3FP 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 139/155頁(yè) |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)當(dāng)前第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)
6-4
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6.2 External bus interface related signals
The M32000D3FP has the following signals related to the external bus.
(1) Address (A8 to A30)
The M32000D3FP has a 24-bit address bus (A8 to A31) corresponding to a 16 MB address space.
Of these, A31 (the LSB) is not output externally. In write cycles, the validity of the two bytes output
_______
on the 16-bit data bus is indicated by BCH and/or BCL. In read cycles, the 16-bit data bus is always
read, however, only data in the valid byte position in the M32000D3FP is transferred.
The address pins are bidirectional. If the M32000D3FP is in the hold state and the internal DRAM
is accessed from an external bus master, the address signal is input from the system bus side. In
this case, A8 to A11 are ignored, however, from the viewpoint of device protection care should be
taken that they are not left open circuit.
(2) Space identifier (SID)
The space identifier is used to specify user space and I/O space (I/O pin).
user space: SID = "L"
I/O space:
SID = "H"
If the M32000D3FP is in the hold state and the internal DRAM is accessed from an external bus
master, the "L" level should be input to SID from the system bus side.
________
(3) Byte control (BCH, BCL)
________
Byte control signals indicate the byte position of valid data transferred of the external bus cycle. BCH
________
corresponds to the MSB side (D0 to D7), and BCL corresponds to the LSB side (D8 to D15). During
________
the bus read cycle, both BCH and BCL are an "L" level. During the bus write cycle, BCH and/or BCL
go to an "L" level depending on the bytes to be written. If the M32000D3FP is in the hold state and
the internal DRAM is accessed from an external bus master, the byte control signal is input from the
system bus side.
(4) Data bus (D0 to D15)
The M32000D3FP has a 16-bit data bus to access external devices. If the M32000D3FP is in the hold
state and the internal DRAM is accessed from an external bus master, the data bus is used as a data
I/O bus from the system bus side.
__
(5) Bus start (BS)
_____
When the M32000D3FP drives the bus cycle to the system bus, an "L" level is output to BS at the
_____
start of the bus cycle. Also, for a burst transfer, the BS signal is output for each transfer cycle. The
_____
BS signal is not output when accessing internal resources such as the internal DRAM or internal I/O
registers.
(6) Bus status (ST)
The ST signal identifies whether the bus cycle the M32000D3FP is driving is an instruction fetch
cycle or an operand access cycle.
instruction fetch access
: ST = "L"
operand access
: ST = "H"
hold
: ST = high-impedance
idle
: ST = undefined
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M32171F2VFP | 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144 |
| M32171F4VFP | 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144 |
| M32176F4TFP | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32176F2TFP | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32180F8TFP | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M32000D4 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 32 BIT CMOS MICROCOMPUTER |
| M32000D4AFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 32 BIT CMOS MICROCOMPUTER |
| M32000D4BFP-80 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER |
| M32002AGLJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO |
| M32002AGMJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, VCXO |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。
