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| 型號： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 107/155頁 |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
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M32000D3FP User's Manual
EIT
4-19
4.9 Interrupt processing
4.9.4 External interrupt (EI)
______
The EI is an interrupt request from the INT pin. It is possible to mask EI events with the IE bit in the PSW
register. For multiple interrupt factors, an external interrupt controller is necessary to manage interrupts.
Furthermore, the EI and the SBI also have the following two functions.
To return the M32000D3FP to normal operation mode from CPU sleep mode.
For details, refer to Chapter 8 "Power management function".
To start the M32000D3FP in slave mode after reset or after returning from standby mode.
For details, refer to Chapter 7 "Master/slave modes".
In both of the above cases, use the EI and limit the use of the SBI only to emergency situations such as
a system breakdown.
[Occurrence condition]
______
The EI occurs when an "L" level is input to the INT pin. The M32R CPU checks the request at the
instruction break point on the word boundary. If there is an interrupt and if the IE bit in the PSW
______
register is "1", the EI is accepted. The INT pin is continously checked when the M32000D3FP is in
CPU sleep mode, or when starting the M32000D3FP after reset or after returning from standby mode.
When starting the M32000D3FP operation set in slave mode, the first external interrupt only is
accepted even when the IE bit in the PSW is "0".
The EI does not start immediately after the 16-bit instruction on the word boundary is executed
(However, with a 16-bit branch instruction, the EI is accepted immediately after branching.).
______
Note: Because the M32R CPU checks the INT pin at the instruction break point on the word
boundary, an "L" level signal should be input continuously when a request is made when in
normal mode. In the case shown below, however, the interrupt request is always accepted
______
when an "L" level signal of 1 CLK width is input to the INT pin, because the INT pin is
continuously monitored under the following conditions:
after reset in slave mode
after returning from standby mode in slave mode
returning from CPU sleep mode.
Fig. 4.9.2 External interrupt (EI) accept timing
16-bit instruction
instruction execution sequence
32-bit instruction
1000
1002
1004
1008
interrupt
accept
O.K.
interrupt
accept
No
16-bit instruction
address
interrupt
accept
O.K.
interrupt
accept
O.K.
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