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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 28/155頁(yè) |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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M32000D3FP User's Manual
RESET
10-3
10.3 Pin condition at reset
Fig. 10.3.1 Pin condition at reset (in master mode)
10.3 Pin condition at reset
_______
The state of the M32000D3FP pins, while "L" level is being input to RST and immediately after "H" level is
_______
input to RST, is as follows.
_______
while an "L" level is being input to RST: undefined
_______
immediately after an "H" level input to RST and for 2 CLKIN periods: idle state
_______
3 CLKIN periods after an "H" level input to RST: the reset vector fetch bus cycle starts
___
However, when the M32000D3FP is in slave mode (M/S = "L"), all pins are in the high-impedance state
during reset, and the vector fetch bus cycle does not start immediately after reset.
Notes 1: Input the reset signal for a minimum of 2 ms after CLKIN input and VCC stabilize.
2: The shaded area is undefined.
3: D0 to D15 and DC are input signal."Hi-z" means high-impedance, and
indicates sampling timing.
4: The above indicated HACK signal state is given for HREQ = "H". When HREQ = "L",
HACK = "L" immediately before and after reset.
The above operation is given for master mode (M/S = "H"). In slave mode (M/S = "L"),
the following pins go to the high-impedance state while reset is in progress.
A8 to A30, D0 to D15, SID, ST, R/W, BCH, BCL, BS, BURST
Further, the vector fetch cycle does not start immediately after reset, and the M32000D3FP enters the
external interrupt input wait state. The bus state after reset depends on the state of the HREQ pin input.
When HREQ = "L": Hold state
When HREQ = "H": Idle state
CLKIN
RST
BCH, BCL
D0 - D15
DC
R/W
more than 2 ms
(see note 1)
idle
vector fetch, operation starts
BS
A8 - A30
SID, ST
(see note 2)
BURST
(see note 2)
HACK
Hi-z
(see note 3)
(see note 4)
q
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