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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 117/155頁(yè) |
| 文件大小： | 1340K |
| 代理商： | M32000D3FP |
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4-28
M32000D3FP User's Manual
EIT
4.13 Interrupt controller example
This interrupt controller automatically performs all of the following interrupt input processing.
(1) Arbitration for interrupt inputs
It compares the priority level previously set for all the input interrupt requests and selects the request
with the highest priority level. If multiple requests have the same priority level, arbitration is based
on the fixed priority of hardware.
______
(2) Interrupt mask decision, INT signal generation and effective vector register setting
It compares the priority level of the selected interrupt request factor and the mask level set in the
mask register. Only when the priority level of the interrupt request is higher than the mask level, the
______
INT signal goes to an "L" level. While INT = "L", the contents of the interrupt vector register (input
request with the highest priority level) are always set in the effective vector register.
(3) Interrupt mask level updating
In the EI handler, it first refers to the effective vector register and branches to the address set there.
Then, it performs processing for each interrupt input.
When the effective vector register is read, the interrupt controller recognizes that the interrupt has
______
been accepted and returns the INT signal to an "H" level. Furthermore, because other interrupts of
the same or lower priority level than the accepted interrupt are masked at this time, the set interrupt
mask level is saved in mask level backup 1, and the interrupt mask level is updated to the same level
as the accepted interrupt.
(4) Mask level return
At the end of processing handler, the request input is cleared which returns the original input mask
level contents saved in mask level backup 1.
With this kind of interrupt controller, if an interrupt request of higher priority is input during interrupt
______
processing, the INT signal is again set to an "L" level. Then, the interrupt mask level is updated and the
effective vector register is set again.
However, the basic EIT operation with the M32000D3FP inhibits multiple interrupts (the IE in the PSW
register is "0" during hardware pre-processing, the original IE is returned in hardware post-processing). For
a system which supports multiple interrupts, it is necessary to set the IE to "1" in the first part of the
interrupt handler and then to "0" in the last part.
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