參數(shù)資料
型號(hào): M32000D3FP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 137/155頁
文件大小: 1340K
代理商: M32000D3FP
6-2
M32000D3FP User's Manual
EXTERNAL BUS INTERFACE
6.1 Bus interface unit (BIU)
The bus interface unit (BIU) controls external bus accesses from the M32000D3FP, and the internal DRAM
accesses from an external bus master. The BIU has a 128-bit data buffer which converts bus width between
the M32000D3FP’s 128-bit internal data bus and the external 16-bit data bus, and also minimizes transfer
times over the internal 128-bit data bus.
6.1.1 External bus access operations
When the M32R CPU accesses the external bus, the BIU controls the external bus and the bus control
signals based on requests from the memory controller.
(1) External bus read operation
When fetching instructions and when the cache memory operation mode is instruction cache mode,
a fixed 8-read (128 bits) burst operation is carried out to replace the cache. After instructions are
accumulated in the BIU’s data buffer, they are transferred to the M32R CPU and cache memory.
When fetching instructions and when cache memory is set to a mode other than instruction cache
mode, a maximum of 8-read (2, 4, 6 or 8 reads) burst operation is carried out for consecutive
addresses within the 128-bit boundary.
To read 32-bit data, burst reading is carried out twice and 32-bit data is transferred to the M32R
CPU.
(2) External bus write operation
To write 32-bit data, 32-bit data placed in the BIU’s data buffer is output to the external bus by a
2-operation burst write.
128-bit
internal data bus
external data bus
(16 bits)
M32000D3FP
BIU
128-bit
data buffer
(bus width conversion)
external bus instruction fetch in instruction cache mode
8 times burst read
8 times (max.) burst read
single or 2-operation burst read
single or 2-operation burst write
cache
memory
DRAM
CPU
external bus instruction fetch in other than instruction cache mode
external bus data read
external bus data write
Fig. 6.1.1 External bus access operations
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