
vi
82801AA and 82801AB
Datasheet
Contents
1
Introduction................................................................................................................1-1
1.1
About this Manual.........................................................................................1-1
1.2
Overview.......................................................................................................1-3
2
Signal Description......................................................................................................2-1
2.1
Hub Interface ................................................................................................2-1
2.2
Firmware Hub Interface ................................................................................2-1
2.3
PCI Interface.................................................................................................2-2
2.4
IDE Interface.................................................................................................2-4
2.5
Low Pin Count (LPC) Interface.....................................................................2-5
2.6
Interrupt Interface .........................................................................................2-6
2.7
USB Interface ...............................................................................................2-6
2.8
Power Management Interface.......................................................................2-7
2.9
Processor Interface.......................................................................................2-8
2.10
SMBus Interface ...........................................................................................2-9
2.11
System Management Interface.....................................................................2-9
2.12
Real Time Clock Interface ............................................................................2-9
2.13
Other Clocks...............................................................................................2-10
2.14
Miscellaneous Signals ................................................................................2-10
2.15
AC’97 Link ..................................................................................................2-10
2.16
General Purpose I/O...................................................................................2-11
2.17
Power and Ground......................................................................................2-12
2.18
Pin Straps...................................................................................................2-12
2.18.1 Functional Strap.............................................................................2-12
2.18.2 Test Straps ....................................................................................2-13
2.18.3 External RTC Circuitry...................................................................2-13
2.18.4 5VREF / Vcc3_3 Sequencing Requirements.................................2-14
3
Power Planes and Pin States....................................................................................3-1
3.1
Power Planes................................................................................................3-1
3.2
Output and I/O Signal Planes and States.....................................................3-1
3.3
Power Planes for Input Signals.....................................................................3-4
3.4
Integrated Pull-Ups and Pull-Downs.............................................................3-5
3.5
IDE Integrated Series Termination Resistors ...............................................3-5
4
Clock Domains...........................................................................................................4-1
5
Functional Description...............................................................................................5-1
5.1
Hub Interface to PCI Bridge (D30:F0)...........................................................5-1
5.1.1
PCI Bus Interface.............................................................................5-1
5.1.2
PCI-to-PCI Bridge Model .................................................................5-1
5.1.3
IDSEL to Device Number Mapping..................................................5-2
5.1.4
SERR#/PERR#/NMI# Functionality.................................................5-2