
Functional Description
5-56
82801AA and 82801AB Datasheet
actual slowdown (and cooling) of the processor depends on the instruction stream, because the
processor is allowed to finish the current instruction. Furthermore, the ICH waits for the
STOP-GRANT cycle before starting the count of the time the STPCLK# signal is active.
When THRM# goes inactive, the throttling stops. However, there is a small window where the ICH
may assert STPCLK# for one more throttling period after THERM# goes inactive.
In case that the ICH is already attempting throttling because the THTL_EN bit is set, the duty cycle
associated with the THRM# signal will have higher priority.
If the ICH is in the C2 or S1-S5 states, then no throttling will be caused by the THRM# signal
being active.
5.12.6.3
Processor Initiated Passive Cooling (Via Programmed Duty Cycle on
STPCLK#)
Using the THTL_EN and THTL_DTY bits, the ICH can force a programmed duty cycle on the
STPCLK# signal. This reduces the effective instruction rate of the processor and cut its power
consumption and heat generation.
5.12.6.4
Active Cooling
Active cooling involves fans. The GPIO signals from the ICH can be used to turn on/off a fan.
5.12.7
Event Input Signals and Their Usage
The ICH has various input signals that trigger specific events. This section describes these signals
and how they should be used.
5.12.7.1
PWRBTN#—Power Button
The ICH PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI
specification. PWRBTN# signal has a 16 ms debounce on the input. The state transition
descriptions are included in
Table 5-42
.
Note:
The transitions start as soon as the PWRBTN# is pressed (but after the debounce logic) and does
not depend on when the Power Button is released.
Table 5-42. Transitions Due to Power Button
Present
State
Event
Transition/Action
Comment
S0/Cx
PWRBTN# goes low
SMI# or SCI generated
(depending on SCI_EN)
Software will typically initiate a
Sleep state.
S1-S5
PWRBTN# goes low
Wake Event. Transitions to S0
state.
Standard wakeup
G3
PWRBTN# pressed
None
No effect since no power.
Not latched nor detected.
S0-S4
PWRBTN# held low for
at least 4 consecutive
seconds
Unconditional transition to S5
state.
No dependence on processor
(such as Stop-Grant cycles) or
any other subsystem.