
82801AA and 82801AB Datasheet
5-65
Functional Description
s
Table 5-48. Alert On LAN Message (ICH: 82801AA only)
Field
Comment
Cover Tamper Status
1 = This bit is set if the intruder detect bit is set (INTRD_DET).
Temp Event Status
1 = This bit is set if the ICH THERM# input signal is asserted.
Processor Missing Event Status
1 = This bit is set if the processor failed to fetch the first instruction.
If the NO-REBOOT bit (D31:F0, Offset D4h, bit 1) is set and the
SECOND_TO_STS bit (TCO I/O offset 06h, bit 1) is set, and the
BOOT_STS bit (TCO I/O offset 06h, bit 2) is set, then the ICH sets
the processor Missing Event Status bit in the Alert On LAN message.
If the NO-REBOOT bit is not set, and the SECOND_TO_STS bit is
set, the ICH attempts to reboot. After the reboot, the
SECOND_TO_STS bit is still set. If the processor fails to fetch the
first instruction, the BOOT_STS bit gets set. When the TCO timer
times out again, the ICH sets the processor Missing Event Status bit
in the Alert On LAN message.
TCO Timer Event Status
1 = This bit is set when the TCO timer expires.
Software Event Status
1 = This bit is set when software writes a 1 to the SEND_NOW bit.
GPIO Status
1 = This bit is set when GPIO[11] signal is low.
0 = This bit is cleared when GPIO[11] signal is high.
An event message is triggered on an transition of GPIO[11].
SEQ[3:0]
This is a sequence number. It is initially 0, and increments each time
the ICH sends a new message. When 1111 is reached, the sequence
number rolls over to 0000. MSB (SEQ3) sent first.
System Power State
00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first
See
Table 5-49
for a definition for each of these states.
MESSAGE1
Same as the MESSAGE1 Register. MSB sent first.
MESSAGE2
Same as the MESSAGE2 Register. MSB sent first.
WDSTATUS
Same as the WDSTATUS Register. MSB sent first.