
82801AA and 82801AB Datasheet
8-67
LPC Interface Bridge Registers (D31:F0)
8.8.3.13
IOMON_STS_EN — I/O Monitor Status and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE +40h
0000h
No
Core
Attribute:
Size:
Usage:
R/W
16 bits
Legacy Only
6
SWSMI_TMR_STS.
1 = Set by the hardware when the Software SMI# Timer expires.
0 = This bit will remain 1 until the software writes a 1 to this bit.
5
APM_STS.
SMI# was generated by a write access to the APM control register and if the APMC_EN
bit is set.
0 = Cleared by writing a 1 to its bit position.
4
SLP_SMI_STS.
1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.
0 = Cleared by software writing a 1 to the bit position.
3
LEGACY_USB_STS.
This non-sticky bit is a logical OR of each of the SMI status bits in the USB
Legacy key board Register ANDed with the corresponding enable bits. This bit will not be active if the
enable bits are not set.
2
BIOS_STS.
SMI# was generated due to ACPI software requesting attention (writing a 1 to the
GBL_RLS bit with the BIOS_EN bit set). This bit is set by hardware and cleared by software writing a
1 to its bit position.
1:0
Reserved.
Bit
Description
Bit
Description
15:14
Reserved
13
IOMON2_STS.
1 = Indicates that the SMI# was caused by an access to the I/O monitor range set in the I/O Monitor
Range 2 Register.
0 = Cleared by writing a 1 to the bit position.
12
IOMON1_STS.
1 = Indicates that the SMI# was caused by an access to the I/O monitor range set in the I/O Monitor
Range 1 Register
0 = Cleared by writing a 1 to the bit position.
11:10
Reserved
9
IOMON2_EN.
1 = Enables the generation of an SMI# upon an access to the I/O monitor range set in the I/O Monitor
Range 2 Register
0 = Disable.
8
IOMON1_EN.
1 = Enables the generation of an SMI# upon an access to the I/O monitor range set in the I/O Monitor
Range 1 Register
0 = Disable
7:0
Reserved