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LPC Interface Bridge Registers (D31:F0)
8-52
82801AA and 82801AB Datasheet
8.8
Power Management Registers (D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as
well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in
the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved
bit, the value should always be 0. Software should not attempt to use the value read from a reserved
bit, as it may not be consistently 1 or 0.
8.8.1
Power Management PCI Configuration Registers (D31:F0)
Table 8-8
shows a small part of the configuration space for PCI Device 31: Function 0. It includes
only those registers dedicated for power management. Some of the registers are only used for
Legacy Power management schemes.
8.8.1.1
GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0)
Offset:
Default Value:
Lockable:
A0h
00h
No
Attribute:
Size:
Usage:
Power Well:
R/W
16 bits
ACPI, Legacy
Core
Table 8-8. PCI Configuration Map (PM—D31:F0)
Offset
Mnemonic
Register Name/Function
Default
Type
40h
–
43h
PMBASE
ACPI Base Address (PMBASE)
00000000h
R/W
44h
ACPI_CNTL
ACPI Control
00h
R/W
A0h
GEN_PMCON_1
General Power Management Configuration 1
0000h
R/W
A2h
GEN_PMCON_2
General Power Management Configuration 2
0000h
R/W
A4h
GEN_PMCON_3
General Power Management Configuration 3
00h
R/W
B8
–
BBh
GPI_ROUT
GPI_ROUT
00000000h
R/W
C4h
IO_MON_RNG1
I/O Monitor Range 1
0000h
R/W
C6h
IO_MON_RNG2
I/O Monitor Range 2
0000h
R/W
CCh
IO_MON_MSK
I/O Monitor Range Mask
0000h
R/W
Bit
Description
15:10
Reserved.
9
PWRBTN_LVL — RO.
This read-only bit indicates the current state of the PWRBTN# signal.
1 = High
0 = Low.
8:6
Reserved.
5
CPUSLP_EN
(CPU SLP# Enable). Enables the CPUSLP# signal to go active in the S1 state. This
reduces the processor power.
ICH (82801AA): For dual processor designs, there will be significant power reduction.
4:0
Reserved.