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xii
82801AA and 82801AB
Datasheet
8.1.24 COM_DEC—LPC I/F Communication Port Decode Ranges
(LPC I/F—D31:F0).........................................................................8-14
8.1.25 FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges
(LPC I/F—D31:F0).........................................................................8-15
8.1.26 SND_DEC—LPC I/F Sound Decode Ranges
(LPC I/F—D31:F0).........................................................................8-15
8.1.27 GEN1_DEC—LPC I/F Generic Decode Range 1
(LPC I/F—D31:F0).........................................................................8-16
8.1.28 GEN2_DEC—LPC I/F Generic Decode Range 2
(LPC I/F—D31:F0).........................................................................8-16
8.1.29 LPC_EN—LPC I/F Enables (LPC I/F—D31:F0)............................8-17
8.1.30 FWH_DEC_EN—FWH Decode Enable Register
(LPC I/F—D31:F0).........................................................................8-18
8.1.31 FWH_SEL—FWH Select Register (LPC I/F—D31:F0)..................8-19
8.1.32 FUNC_DIS—Function Disable Register (LPC I/F—D31:F0).........8-20
DMA I/O Registers......................................................................................8-21
8.2.1
DMABASE_CA—DMA Base and Current Address Registers.......8-22
8.2.2
DMABASE_CC—DMA Base and Current Count Registers...........8-23
8.2.3
DMAMEM_LP—DMA Memory Low Page Registers .....................8-23
8.2.4
DMACMD—DMA Command Register...........................................8-24
8.2.5
DMASTA—DMA Status Register...................................................8-24
8.2.6
DMA_WRSMSK—DMA Write Single Mask Register.....................8-25
8.2.7
DMACH_MODE—DMA Channel Mode Register...........................8-25
8.2.8
DMA Clear Byte Pointer Register ..................................................8-26
8.2.9
DMA Master Clear Register...........................................................8-26
8.2.10 DMA_CLMSK—DMA Clear Mask Register ...................................8-26
8.2.11 DMA_WRMSK—DMA Write All Mask Register.............................8-27
Timer I/O Registers.....................................................................................8-28
8.3.1
TCW—Timer Control Word Register .............................................8-28
8.3.1.1
RDBK_CMD—Read Back Command ............................8-29
8.3.1.2
LTCH_CMD—Counter Latch Command........................8-30
8.3.2
SBYTE_FMT—Interval Timer Status Byte Format Register..........8-30
8.3.3
Counter Access Ports Register......................................................8-31
8259 Interrupt Controller (PIC) Registers ...................................................8-32
8.4.1
Interrupt Controller I/O MAP ..........................................................8-32
8.4.2
ICW1—Initialization Command Word 1 Register...........................8-33
8.4.3
ICW2—Initialization Command Word 2 Register...........................8-34
8.4.4
ICW3—Master Controller Initialization Command
Word 3 Register.............................................................................8-34
8.4.5
ICW3—Slave Controller Initialization Command
Word 3 Register.............................................................................8-35
8.4.6
ICW4—Initialization Command Word 4 Register...........................8-35
8.4.7
OCW1—Operational Control Word 1 (Interrupt Mask) Register....8-35
8.4.8
OCW2—Operational Control Word 2 Register ..............................8-36
8.4.9
OCW3—Operational Control Word 3 Register ..............................8-37
8.4.10 ELCR1—Master Controller Edge/Level Triggered Register ..........8-38
8.4.11 ELCR2—Slave Controller Edge/Level Triggered Register ............8-38
8.2
8.3
8.4