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82801AA and 82801AB Datasheet
10-7
USB Controller Registers (D31:F2)
10.1.17
USB_RES—USB Resume Enable Register (USB—D31:F2)
Address Offset:
Default Value:
C4h
00h
Attribute:
Size:
R/W
8 bits
8
SMI Caused by Port 60 Read (TRAPBY60R).
Indicates if the event occurred. Note that even if the
corresponding enable bit is not set in the Bit 0, then this bit will still be active. It is up to the SMM code
to use the enable bit to determine the exact cause of the SMI#.
1 = Event Occurred
0 = Cleared by writing a 1 to it.
7
SMI at End of Pass-through Enable (SMIATENDPS).
May need to cause SMI at the end of a pass-
through. Can occur if an SMI is generated in the middle of a pass through, and needs to be serviced
later.
6
Pass Through State (PSTATE).
1= Indicates that the state machine is in the middle of an A20GATE pass-through sequence.
0 = If software needs to reset this bit, it should set Bit 5 to 0.
5
A
20Gate Pass-Through Enable (A20PASSEN).
1 = Enable. Allows A20GATE sequence Pass-Through function (see details below). SMI# is not
generated, even if the various enable bits are set.
0 = Disable.
4
SMI on USB IRQ (USBSMIEN).
1 = USB interrupt cause an SMI event.
3
SMI on Port 64 Writes Enable (64WEN).
1 = Write to port 64h cause an SMI event.
2
SMI on Port 64 Reads Enable (64REN).
1 = Read to port 64h cause an SMI event.
1
SMI on Port 60 Writes Enable (60WEN).
1 = Write to port 60h cause an SMI event.
0
SMI on Port 60 Reads Enable (60REN).
1 = Read to port 60h cause an SMI event.
Bit
Description
Bit
Description
7:2
Reserved.
1
PORT1EN.
Enable port 1 of the USB controller to look at wakeup events.
1 = The USB controller monitors port 1 for remote wakeup and connect/disconnect events.
0 = The USB controller will not look at this port for a wakeup event.
0
PORT0EN.
Enable port 0 of the USB controller to look at wakeup events.
1 = the USB controller monitors port 0 for remote wakeup and connect/disconnect events.
0 = The USB controller does not look at this port for a wakeup event.