
Register Index
A-14
82801AA and 82801AB Datasheet
USB I/O Registers at Base Address + Offset
USB Base Address is set at Section 10.1.10, “BASE—Base Address Register (USB—D31:F2)” on
page 10-4
USB Command Register
00h–01h
Section 10.2.1, “USBCMD—USB Command
Register” on page 10-8
USB Status Register
02h–03h
Section 10.2.2, “USBSTA—USB Status Register” on
page 10-11
USB Interrupt Enable
04h–05h
Section 10.2.3, “USBINTR—Interrupt Enable
Register” on page 10-12
USB Frame Number
06h–07h
Section 10.2.4, “FRNUM—Frame Number Register”
on page 10-12
USB Frame List Base Address
08h–0Bh
Section 10.2.5, “FRBASEADD—Frame List Base
Address” on page 10-13
USB Start of Frame Modify
0Ch
Section 10.2.6, “SOFMOD—Start of Frame Modify
Register” on page 10-13
Port 0 Status/Control
10h–11h
Section 10.2.7, “PORTSC[0,1]—Port Status and
Control Register” on page 10-14
Port 1 Status/Control
12h–13h
Section 10.2.7, “PORTSC[0,1]—Port Status and
Control Register” on page 10-14
Loop Back Test Data
18h
SMBus I/O Registers at SMB_BASE + Offset
SMB_BASE is set at
Section 11.1.10, “SMB_BASE—SMBus Base Address Register (SMBUS—D31:F3)” on
page 11-4
Host Status
00h
Section 11.2.1, “HST_STA—Host Status Register” on
page 11-7
Host Control
02h
Section 11.2.2, “HST_CNT—Host Control Register”
on page 11-8
Host Command
03h
Section 11.2.3, “HST_CMD—Host Command
Register” on page 11-9
Transmit Slave Address
04h
Section 11.2.4, “XMIT_SLVA—Transmit Slave
Address Register” on page 11-9
Host Data 0
05h
Section 11.2.5, “D0—Data 0 Register” on page 11-9
Host Data 1
06h
Section 11.2.6, “D1—Data 1 Register” on page 11-9
Block Data Byte
07h
Section 11.2.7, “BLOCK_DB—Block Data Byte
Register” on page 11-10
AC’97 Audio I/O Registers at NAMBAR + Offset
NAMBAR is set at Section 12.1.10, “NAMBAR—Native Audio Mixer Base Address Register (Audio—
D31:F5)” on page 12-5
PCM In Buffer Descriptor list Base
Address Register
00h
Section 12.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 12-10
PCM In Current Index Value
04h
Section 12.2.2, “x_CIV—Current Index Value
Register” on page 12-10
PCM In Last Valid Index
05h
Section 12.2.3, “x_LVI—Last Valid Index Register” on
page 12-10
PCM In Status Register
06h
Section 12.2.4, “x_SR—Status Register” on
page 12-11
Table A-3. ICH Variable I/O Registers (Sheet 3 of 5)
Register Name
Offset
Datasheet Section and Location