
Signal Description
2-10
82801AA and 82801AB Datasheet
2.13
Other Clocks
2.14
Miscellaneous Signals
2.15
AC’97 Link
These signals are for Device 31:Functions 5 and 6.
.
Table 2-13. Other Clocks
Name
Type
Description
CLK14
I
Oscillator Clock:
Used for 8254 timers. Runs at 14.31818 MHz. This clock is permitted
to stop during S3 (or lower) states.
CLK48
I
48 MHz Clock:
Used to run the USB controller. Runs at 48 MHz. This clock is permitted
to stop during S3 (or lower) states.
CLK66
I
66 MHz Clock:
Used to run the hub interface. Runs at 66 MHz. This clock is permitted to
stop during S3 (or lower) states.
Table 2-14. Miscellaneous Signals
Name
Type
Description
SPKR
O
Speaker:
The SPKR signal is the output of counter 2 and is internally "ANDed" with
Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker
driver device, which in turn drives the system speaker. Upon PCIRST#, its output state
is 1.
Note: SPKR is sampled at the rising edge of PWROK as a functional strap. See
Section 2.18.1
for more details.
RTCRST#
I
RTC Reset:
When asserted, this signal resets register bits in the RTC well and sets the
RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). This signal is also used to enter
the test modes documented in
Section 2.18.2
.
Table 2-15. AC’97 Link Signals
Name
Type
Description
AC_RST#
O
AC97 Reset:
Master H/W reset to external Codec(s)
AC_SYNC
O
AC97 Sync:
48 KHz fixed rate sample sync to the Codec(s)
AC_BIT_CLK
I
AC97 Bit Clock:
12.288 MHz serial data clock generated by the external Codec(s)
AC_SDOUT
O
AC97 Serial Data Out:
Serial TDM data output to the Codec(s)
Note: AC_SDOUT is sampled at the rising edge of PWROK as a functional strap.
See
Section 2.18.1
for more details.
AC_SDIN 0
I
AC97 Serial Data In 0:
Serial TDM data input from a Codec
AC_SDIN 1
/
GPIO[9]
I
AC97 Serial Data In 1:
Serial TDM data input from a Codec.
Note: If a separate codec is not used, this signal can be used as a GPI.