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82801AA and 82801AB Datasheet
5-55
Functional Description
The ICH monitors both PWROK and RSMRST# to detect for power failures. If PWROK goes low,
the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Note:
Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss.
PME_EN and PME_STS bits are cleared by RSMRST#
5.12.6
Thermal Management
The ICH has mechanisms to assist with managing thermal problems in the system.
5.12.6.1
THRM# Signal
The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal
going active, the ICH generates an SMI# or SCI (depending on SCI_EN).
If the THRM_POL bit is cleared to “0”, when the THRM# signal goes low, the THRM_STS bit is
set to “1”. This is an indicator that the thermal threshold has been exceeded. If the THRM_EN bit
is set, then when THRM_STS goes active, either an SMI# or SCI is generated (depending on the
SCI_EN bit being set).
The power management software (BIOS or ACPI) can then take measures to start reducing the
temperature. Examples include shutting off unwanted subsystems, or halting the processor.
By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated when the
THRM# signal goes back low. This allows the software (BIOS or ACPI) to turn off the cooling
methods.
5.12.6.2
THRM# Initiated Passive Cooling
If the THRM# signal remains active for some time greater than 2 seconds and the ICH is in the
S0/G0/C0 state, then the ICH enters an auto-throttling mode, in which it provides a duty cycle on
the STPCLK# signal. This reduces the overall power consumption by the system, and should cool
the system. The intended result of the cooling is that the THRM# signal should go back inactive.
For all programmed values (001 - 111), THRM# going active results in STPCLK# active for a
minimum time of 12.5% and a maximum of 87.5%. The period is 1024 PCI clocks. Thus, the
STPCLK# signal can be active for as little as 128 PCI clocks or as much as 896 PCI clocks. The
Table 5-41. Transitions Due To Power Failure
State at Power Failure
AFTERG3_EN bit
Transition When Power Returns
S0
1
0
S5
S0
S1
1
0
S5
S0
S3
1
0
S5
S0
S4
1
0
S4
S0
S5
1
0
S5
S0