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82801AA and 82801AB Datasheet
5-115
Functional Description
Writes to offset 54h and D4h (primary and secondary codecs) get transmitted across the AC-link in
slots 1 and 2 as a normal register access. Slot 12 is also updated immediately to reflect the data
being written.
The controller does not issue back to back reads. It must get a response to the first read before
issuing a second. In addition, codec reads and writes are only executed once across the link and are
not repeated.
5.18
AC-Link Low Power Mode
The AC-link signals can be placed in a low power mode. When the AC‘97 Powerdown Register
(26h) is programmed to the appropriate value, both BIT_CLK and SDIN will be brought to and
held at a logic low voltage level.
BIT_CLK and SDIN transition low immediately following a write to the Powerdown Register
(26h) with PR4. When the AC‘97 controller driver is at the point where it is ready to program the
AC-link into its low power mode, slots 1 and 2 are assumed to be the only valid stream in the audio
output frame.
The AC‘97 controller also drives AC_SYNC, and SDOUT low after programming AC‘97 to this
low power, halted mode
Once the codec has been instructed to halt BIT_CLK, a special wake up protocol must be used to
bring the AC-link to the active mode since normal output and input frames can not be
communicated in the absence of BIT_CLK. Once in a low power mode, the ICH provides three
methods for waking up the AC-link; external wake event, cold reset, and warm reset
Note:
Before entering any low power mode where the link interface to the codec is expected to be
powered down while the rest of the system is awake, the software must set the "Shut Off" bit to 1 in
the control register.
Figure 5-20. AC-link Powerdown Timing
SDOUT
TAG
SYNC
BIT_CLK
Write to
0x20
Data
PR4
slot 12
prev. frame
TAG
slot 12
prev. frame
SDIN
Note:
BIT_CLK not to scale