
82801AA and 82801AB Datasheet
5-57
Functional Description
Power Button Override:
If PWRBTN# is observed active for at least 4 consecutive seconds, then
the state machine unconditionally transitions to the G2/S5 state, regardless of present state (S0-S4).
In this case, the transition to the G2/S5 state does not depend on any particular response from the
processor (such as a Stop-Grant cycle), nor any similar dependency from any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or has been
released. The status is taken after the debounce, and is readable via the PWRBTN_LVL bit.
Note:
The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The
4-second timer starts counting when the ICH is in a S0 state. If the PWRBTN# signal is asserted
and held active when the system is in a suspend state (S1-S5), the assertion causes a wake event.
Once the system has resumed to the S0 state, the 4-second timer starts.
Sleep Button:
The ACPI specification defines an optional Sleep button. It differs from the power
button in that it only is a request to go from S0 to S1-S4 (not S5). Also, in an S5 state, the Power
Button can wake the system, but the Sleep Button cannot.
Although the ICH does not include a specific signal designated as a Sleep Button, one of the GPIO
signals can be used to create a “Control Method” Sleep Button. This requires some AML code to
be developed. Example code is provided in the ACPI specification.
5.12.7.2
RI#—Ring Indicate
The Ring Indicator can cause a wake event (if enabled) from the S1-S5 states.
Table 5-43
shows
when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the
UART is configured to cause an interrupt based on RI# active, and the interrupt will be set up as a
break event.
Filtering/Debounce on RI# is not be done in ICH. This can be in the modem or external.
5.12.7.3
PME#—PCI Power Management Event
The PME# signal comes from a PCI device to request that the system be restarted. The PME#
signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME#
signal goes from high to low. No event is caused when PME# goes from low to high.
5.12.8
Alt Access Mode
Before entering a low power state, several registers from powered down parts may need to be
saved. In the majority of cases, this is not an issue, as registers have read and write paths. However,
several of the ISA compatible registers are either read only or write only. To get data out of write-
only registers, and to restore data into read-only registers, the ICH implements an alternate access
mode.
Table 5-43. Transitions Due to RI# Signal
Present State
Event
RI_EN
Event
S0
RI# Active
X
0
1
Ignored
Ignored
Wake Event
S1-S5
RI# Active