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82801AA and 82801AB Datasheet
6-5
Register and Memory Mapping
NOTES:
1. Only if IDE Standard I/O space is enabled for Primary Drive. Otherwise, the target is PCI.
2. Only if IDE Standard I/O space is enabled for Secondary Drive. Otherwise, the target is PCI.
3. If POS_DEC_EN bit is enabled, reads from F0h will not be decoded by the ICH. If POS_DEC_EN is not
enabled, reads from F0h will forward to LPC.
77h
RTC Controller
RTC Controller
RTC
80h
DMA Controller
DMA Controller and LPC or PCI
DMA
81h–83h
DMA Controller
DMA Controller
DMA
84h–86h
DMA Controller
DMA Controller and LPC or PCI
DMA
87h
DMA Controller
DMA Controller
DMA
88h
DMA Controller
DMA Controller and LPC or PCI
DMA
89h–8Bh
DMA Controller
DMA Controller
DMA
8Ch–8Eh
DMA Controller
DMA Controller and LPC or PCI
DMA
08Fh
DMA Controller
DMA Controller
DMA
92h
Reset Generator
Reset Generator
Processor Interface
A0h–A1h
Interrupt Controller
Interrupt Controller
Interrupt
A4h–A5h
Interrupt Controller
Interrupt Controller
Interrupt
A8h–A9h
Interrupt Controller
Interrupt Controller
Interrupt
ACh–ADh
Interrupt Controller
Interrupt Controller
Interrupt
B0h–B1h
Interrupt Controller
Interrupt Controller
Interrupt
B2h–B3h
Power Management
Power Management
TBD
B4h–B5h
Interrupt Controller
Interrupt Controller
Interrupt
B8h–B9h
Interrupt Controller
Interrupt Controller
Interrupt
BCh–BDh
Interrupt Controller
Interrupt Controller
Interrupt
C0h–D1h
DMA Controller
DMA Controller
DMA
D2h–DDh
Reserved
DMA Controller
DMA
DEh–DFh
DMA Controller
DMA Controller
DMA
F0h
See Note 3
FERR#/IGNNE#/ Interrupt
Controller
Processor Interface
170h–177h
IDE Controller
1
IDE Controller
1
IDE
1F0h–1F7h
IDE Controller
2
IDE Controller
2
IDE
376h
IDE Controller
1
IDE Controller
1
IDE
3F6h
IDE Controller
2
IDE Controller
2
IDE
4D0h–4D1h
Interrupt Controller
Interrupt Controller
IDE
CF9h
Reset Generator
Reset Generator
Processor Interface
Table 6-3. Fixed I/O Ranges Decoded by ICH (Sheet 2 of 2)
I/O Address
Read Target
Write Target
Internal Unit