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Register Index
A-2
82801AA and 82801AB Datasheet
I/O Limit Upper 16 Bits
32h–33h
Section 7.1.22, “IOLIM_HI—I/O Limit Upper 16 Bits
Register (HUB-PCI—D30:F0)” on page 7-10
Section 7.1.23, “INT_LINE—Interrupt Line Register
(HUB-PCI—D30:F0)” on page 7-10
Section 7.1.24, “BRIDGE_CNT—Bridge Control
Register (HUB-PCI—D30:F0)” on page 7-11
Section 7.1.25, “CNF—ICH Configuration Register
(HUB-PCI—D30:F0)” on page 7-12
Section 7.1.26, “MTT—Multi-Transaction Timer Register
(HUB-PCI—D30:F0)” on page 7-13
Section 7.1.27, “PCI_MAST_STS—PCI Master Status
Register (HUB-PCI—D30:F0)” on page 7-13
Section 7.1.28, “ERR_CMD—Error Command Register
(HUB-PCI—D30:F0)” on page 7-14
Section 7.1.29, “ERR_STS—Error Status Register
(HUB-PCI—D30:F0)” on page 7-14
Interrupt Line
3Ch
Bridge Control
3Eh–3Fh
ICH Configuration Register
50h–51h
Multi-Transaction Timer
70h
PCI Master Status
82h
Error Command Register
90h
Error Status Register
92h
LPC Bridge D31:F0
Vendor ID
00h–01h
Section 8.1.1, “VID—Vendor ID Register (LPC I/F—
D31:F0)” on page 8-2
Section 8.1.2, “DID—Device ID Register (LPC I/F—
D31:F0)” on page 8-2
Section 8.1.3, “PCICMD—PCI COMMAND Register
(LPC I/F—D31:F0)” on page 8-3
Section 8.1.4, “PCISTA—PCI Device Status (LPC I/F—
D31:F0)” on page 8-4
Section 8.1.5, “RID—Revision ID Register (LPC I/F—
D31:F0)” on page 8-5
Section 8.1.6, “PI—Programming Interface (LPC I/F—
D31:F0)” on page 8-5
Section 8.1.7, “SCC—Sub-Class Code Register (LPC I/
F—D31:F0)” on page 8-5
Section 8.1.8, “BCC—Base-Class Code Register (LPC I/
F—D31:F0)” on page 8-5
Section 8.1.9, “HEADTYP—Header Type Register (LPC
I/F—D31:F0)” on page 8-5
Section 8.1.10, “PMBASE—ACPI Base Address (LPC I/
F—D31:F0)” on page 8-6
Section 8.1.11, “ACPI_CNTL—ACPI Control (LPC I/F —
D31:F0)” on page 8-6
Section 8.1.12, “BIOS_CNTL (LPC I/F—D31:F0)” on
page 8-7
Section 8.1.13, “TCO_CNTL — TCO Control (LPC I/F —
D31:F0)” on page 8-7
Section 8.1.14, “GPIOBASE—GPIO Base Address
(LPC I/F—D31:F0)” on page 8-8
Section 8.1.15, “GPIO_CNTL—GPIO Control (LPC I/F—
D31:F0)” on page 8-8
Section 8.1.16, “PIRQ[n]_ROUT—PIRQ[A,B,C,D]
Routing Control (LPC I/F—D31:F0)” on page 8-9
Section 8.1.17, “SERIRQ_CNTL—Serial IRQ Control
(LPC I/F—D31:F0)” on page 8-9
Section 8.1.18, “D31_ERR_CFG—Device 31 Error
Config Register (LPC I/F—D31:F0)” on page 8-10
Device ID
02h–03h
PCI Command Register
04h–05h
PCI Device Status Register
06h–07h
Revision ID
08h
Programming Interface
09h
Sub Class Code
0Ah
Base Class Code
0Bh
Header Type
0Eh
ACPI Base Address Register
40h–43h
ACPI Control
44h
BIOS Control Register
4Eh–4Fh
TCO Control
54h
GPIO Base Address Register
58h–5Bh
GPIO Control Register
5Ch
PIRQ[A-D] Routing Control
60h–63h
Serial IRQ Control Register
64h
Device 31 Error Config Register
88h
Table A-1. ICH PCI Configuration Registers (Sheet 2 of 7)
Register Name
Offset
Datasheet Section and Location