
82801AA and 82801AB Datasheet
A-11
Register Index
NOTE:
When the POS_DEC_EN bit is set, additional I/O ports get positively decoded by the ICH. Refer to
Section 8.1.24
through
Section 8.1.29
for a listing of these ranges.
Aliased at C8h
Channel 6 DMA Base & Current
Count Register
Aliased at CAh
Channel 7 DMA Base & Current
Address Register
Aliased at CCh
Channel 7 DMA Base & Current
Count Register
Aliased at CEh
C9h
CAh
Section 8.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 8-23
CBh
CCh
Section 8.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 8-22
CDh
CEh
Section 8.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 8-23
CFh
Channel 4-7 DMA Command
Register
Channel 4-7 DMA Status Register
D0h
Section 8.2.4, “DMACMD—DMA Command Register”
on page 8-24
Section 8.2.5, “DMASTA—DMA Status Register” on
page 8-24
Aliased at D0h
Channel 4-7 DMA Write Single
Mask Register
Aliased at D4h
Channel 4-7 DMA Channel Mode
Register
Aliased at D6h
Channel 4-7 DMA Clear Byte
Pointer Register
Aliased at D8h
Channel 4-7 DMA Master Clear
Register
Aliased at DAh
Channel 4-7 DMA Clear Mask
Register
Aliased at DCh
Channel 4-7 DMA Write All Mask
Register
Aliased at DEh
D1h
D4h
Section 8.2.6, “DMA_WRSMSK—DMA Write Single
Mask Register” on page 8-25
D5h
D6h
Section 8.2.7, “DMACH_MODE—DMA Channel Mode
Register” on page 8-25
D7h
D8h
Section 8.2.8, “DMA Clear Byte Pointer Register” on
page 8-26
D9h
DAh
Section 8.2.9, “DMA Master Clear Register” on
page 8-26
DBh
DCh
Section 8.2.10, “DMA_CLMSK—DMA Clear Mask
Register” on page 8-26
DEh
DEh
Section 8.2.11, “DMA_WRMSK—DMA Write All Mask
Register” on page 8-27
DFh
Coprocessor Error Reigster
F0h
Section 8.7.4, “COPROC_ERR—Coprocessor Error
Register” on page 8-50
PIO Mode Command Block Offset
for Secondary Drive
PIO Mode Command Block Offset
for Primary Drive
PIO Mode Control Block Offset for
Secondary Drive
PIO Mode Control Block Offset for
Primary Drive
Master PIC Edge/Level Triggered
Register
Slave PIC Edge/Level Triggered
Register
170h–177h
See ATA Specification for detailed register description
1F0h–1F7h
See ATA Specification for detailed register description
376h
See ATA Specification for detailed register description
3F6h
See ATA Specification for detailed register description
4D0h
Section 8.4.10, “ELCR1—Master Controller Edge/Level
Triggered Register” on page 8-38
Section 8.4.11, “ELCR2—Slave Controller Edge/Level
Triggered Register” on page 8-38
Section 8.7.5, “RST_CNT—Reset Control Register” on
page 8-51
4D1h
Reset Control Register
CF9h
Table A-2. ICH Fixed I/O Registers (Sheet 4 of 4)
Register Name
Port
Datasheet Section and Location