
82801AA and 82801AB Datasheet
A-13
Register Index
TCO I/O Registers at TCOBASE + Offset
TCOBASE = PMBASE + 60h
PMBASE is set in
Section 8.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 8-6
TCO_RLD: TCO Timer Reload and
Current Value
00h
Section 8.9.2, “TCO1_RLD—TCO Timer Reload and
Current Value” on page 8-70
TCO_TMR: TCO Timer Initial Value
01h
Section 8.9.3, “TCO1_TMR—TCO Timer Initial Value”
on page 8-70
TCO_DAT_IN: TCO Data In
02h
Section 8.9.4, “TCO1_DAT_IN—TCO Data In
Register” on page 8-71
TCO_DAT_OUT: TCO Data Out
03h
Section 8.9.5, “TCO1_DAT_OUT—TCO Data Out
Register” on page 8-71
TCO1_STS : TCO Status
04h–05h
Section 8.9.6, “TCO1_STS—TCO1 Status Register”
on page 8-71
TCO2_STS : TCO Status
06h–07h
Section 8.9.7, “TCO2_STS—TCO2 Status Register”
on page 8-72
TCO1_CNT: TCO Control
08h–09h
Section 8.9.8, “TCO1_CNT—TCO1 Control Register”
on page 8-73
TCO2_CNT: TCO Control
0Ah–0Bh
Section 8.9.9, “TCO2_CNT—TCO2 Control Register”
on page 8-73
GPIO I/O Registers at GPIOBASE + Offset
GPIOBASE is set in
Section 8.1.14, “GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)” on page 8-8
GPIO Use Select
00h–03h
Section 8.10.2, “GPIO_USE_SEL—GPIO Use Select
Register” on page 8-79
GPIO Input/Output Select
04h–07h
Section 8.10.3, “GP_IO_SEL—GPIO Input/Output
Select Register” on page 8-80
GPIO Level for Input or Output
0Ch–0Fh
Section 8.10.4, “GP_LVL—GPIO Level for Input or
Output Register” on page 8-81
GPIO TTL Select
14h–17h
Section 8.10.5, “GPO_TTL—GPIO TTL Select
Register” on page 8-81
GPIO Blink Enable
18h–1Bh
Section 8.10.6, “GPO_BLINK—GPO Blink Enable
Register” on page 8-82
GPIO Signal Invert
2Ch–2Fh
Section 8.10.7, “GPI_INV—GPIO Signal Invert
Register” on page 8-82
BMIDE I/O Registers at BM_BASE + Offset
BM_BASE is set at
Section 9.1.11, “BM_BASE—Bus Master Base Address Register (IDE—D31:F1)” on
page 9-5
Command Register Primary
00h
Section 9.2.1, “BMIC[P,S]—Bus Master IDE
Command Register” on page 9-12
Status Register Primary
02h
Section 9.2.2, “BMIS[P,S]—Bus Master IDE Status
Register” on page 9-13
Descriptor Table Pointer Primary
04h–07h
Section 9.2.3, “BMID[P,S]—Bus Master IDE
Descriptor Table Pointer Register” on page 9-13
Command Register Secondary
08h
Section 9.2.1, “BMIC[P,S]—Bus Master IDE
Command Register” on page 9-12
Status Register Secondary
0Ah
Section 9.2.2, “BMIS[P,S]—Bus Master IDE Status
Register” on page 9-13
Descriptor Table Pointer Secondary
0Ch–0Fh
Section 9.2.3, “BMID[P,S]—Bus Master IDE
Descriptor Table Pointer Register” on page 9-13
Table A-3. ICH Variable I/O Registers (Sheet 2 of 5)
Register Name
Offset
Datasheet Section and Location