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參數(shù)資料
| 型號(hào)： | INTELDX2 |
| 廠商： | Intel Corp. |
| 英文描述： | High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器) |
| 中文描述： | 高性能32位嵌入式處理器（高性能32位嵌入式處理器） |
| 文件頁(yè)數(shù)： | 1/48頁(yè) |
| 文件大?。?/td> | 486K |
| 代理商： | INTELDX2 |
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INTEL CORPORATION, 1997
December 1997
Order Number:
272770-002
EMBEDDED IntelDX2 PROCESSOR
Figure 1.
Embedded IntelDX2 Processor Block Diagram
I
Integrated Floating-Point Unit
I
Speed-Multiplying Technology
I
32-Bit RISC Technology Core
I
8-Kbyte Write-Through Cache
I
Four Internal Write Buffers
I
Burst Bus Cycles
I
Dynamic Bus Sizing for 8- and 16-bit
Data Bus Devices
I
SL Technology
I
Data Bus Parity Generation and Checking
I
Boundary Scan (JTAG)
I
3.3-Volt Processor, 50 MHz, 25 MHz CLK
— 208-Lead Shrink Quad Flat Pack (SQFP)
I
5-Volt Processor, 66 MHz, 33 MHz CLK
— 168-Pin Pin Grid Array (PGA)
I
Binary Compatible with Large Software
Base
Paging
Unit
Prefetcher
32-Byte Code
Queue
2x16 Bytes
Code
Stream
Floating
Point Unit
Barrel
Shifter
24
Cache Unit
Burst Bus
Control
Bus Control
Write Buffers
4 x 32
64-Bit Interunit Transfer Bus
Register
File
ALU
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
32
Base/
Index
Bus
Translation
Lookaside
Buffer
20
8 Kbyte
Cache
Clock
Multiplier
Floating
Point
Register File
Control &
Protection
Test Unit
Control
ROM
Address
Drivers
CLK
Core
Clock
32
32
Data Bus
Transceivers
32
Request
Sequencer
Bus Size
Control
Cache
Control
Parity
Generation
and Control
Boundary
Scan
Control
Bus Interface
D31-D0
A31-A2
BE3#- BE0#
ADS# W/R# D/C# M/IO#
PCD PWT RDY# LOCK#
PLOCK# BOFF# A20M#
BREQ HOLD HLDA
RESET SRESET INTR
NMI SMI# SMIACT#
FERR# IGNNE#
STPCLK#
A3223-01
BRDY# BLAST#
BS16# BS8#
KEN# FLUSH#
AHOLD EADS#
DP3-DP0 PCHK#
TCK TMS
TDI TD0
1
Instruction
Decode
32
Decoded
PCD
PWT
2
Physical
Address
32-Bit Data Bus
32-Bit Data Bus
Linear Address
InMicro-
Displacement Bus
32
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