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| 型號： | INTELDX2 |
| 廠商： | Intel Corp. |
| 英文描述： | High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器) |
| 中文描述： | 高性能32位嵌入式處理器（高性能32位嵌入式處理器） |
| 文件頁數(shù)： | 7/48頁 |
| 文件大小： | 486K |
| 代理商： | INTELDX2 |
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Embedded IntelDX2 Processor
3
2.0
HOW TO USE THIS DOCUMENT
For a complete set of documentation related to the
embedded IntelDX2 processor, use this document in
conjunction with the following reference documents:
Embedded Intel486 Processor Family
Developer’s Manual — Order No. 273021
Embedded Intel486 Processor Hardware
Reference Manual — Order No. 273025
Intel486 Microprocessor Family Programmer’s
Reference Manual— Order No. 240486
Intel Application Note AP-485 —
Intel Processor
Identification with the CPUID Instruction
—
Order No. 241618
The information in the reference documents for the
IntelDX2 processor applies to the embedded
IntelDX2 processor. Some of the IntelDX2 processor
information is duplicated in this document to
minimize the dependence on the reference
documents.
3.0
PIN DESCRIPTIONS
3.1
Pin Assignments
The following figures and tables show the pin assign-
ments of each package type for the embedded
IntelDX2 processor. Tables are provided showing
the pin differences between the embedded IntelDX2
processor and other embedded Intel486 processor
products.
208-Lead SQFP - Quad Flat Pack
Figure 2, Package Diagram for 208-Lead SQFP
Embedded IntelDX2 Processor (pg. 4)
Table 2, Pinout Differences for 208-Lead SQFP
Package (pg. 5)
Table 3, Pin Assignment for 208-Lead SQFP
Package (pg. 6)
Table 4, Pin Cross Reference for 208-Lead SQFP
Package (pg. 8)
168-Pin PGA - Pin Grid Array
Figure 3, Package Diagram for 168-Pin PGA
Embedded IntelDX2 Processor (pg. 10)
Table 5, Pinout Differences for 168-Pin PGA
Package (pg. 11)
Table 6, Pin Assignment for 168-Pin PGA
Package (pg. 12)
Table 7, Pin Cross Reference for 168-Pin PGA
Package (pg. 14)
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