
Contents
iv
Figure 12.
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition, 3.3 V Processor .........................................................................39
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition, 3.3 V Processor .........................................................................39
Typical Loading Delay versus Load Capacitance under
Worst-Case Conditions for a Low-to-High Transition, 5 V Processor ......................................40
Typical Loading Delay versus Load Capacitance under
Worst-Case Conditions for a High-to-Low Transition, 5 V Processor ......................................40
208-Lead SQFP Package Dimensions .................................................................................... 41
Principal Dimensions and Data for 168-Pin Pin Grid Array Package .......................................42
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
The Embedded IntelDX2
Processor Family ............................................................................2
Pinout Differences for 208-Lead SQFP Package ......................................................................5
Pin Assignment for 208-Lead SQFP Package ...........................................................................6
Pin Cross Reference for 208-Lead SQFP Package ...................................................................8
Pinout Differences for 168-Pin PGA Package .........................................................................11
Pin Assignment for 168-Pin PGA Package ..............................................................................12
Pin Cross Reference for 168-Pin PGA Package ......................................................................14
Embedded IntelDX2 Processor Pin Descriptions .................................................................16
Output Pins ..............................................................................................................................23
Input/Output Pins .....................................................................................................................23
Test Pins ..................................................................................................................................23
Input Pins .................................................................................................................................24
CPUID Instruction Description .................................................................................................25
Boundary Scan Component Identification Code (3.3 Volt Processor) .....................................26
Boundary Scan Component Identification Code (5 Volt Processor) ........................................27
Absolute Maximum Ratings .....................................................................................................28
Operating Supply Voltages ......................................................................................................28
3.3 V DC Specifications ...........................................................................................................29
3.3 V I
CC
Values ......................................................................................................................30
5 V DC Specifications ..............................................................................................................31
5 V I
CC
Values .........................................................................................................................32
AC Characteristics ...................................................................................................................33
AC Specifications for the Test Access Port .............................................................................34
168-Pin Ceramic PGA Package Dimensions ...........................................................................42
Ceramic PGA Package Dimension Symbols ...........................................................................43
Thermal Resistance,
θ
JA
(
°
C/W) .............................................................................................44
Thermal Resistance,
θ
JC
(
°
C/W) .............................................................................................44
Maximum T
ambient
, T
A
max (
°
C) ...............................................................................................44