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參數(shù)資料
| 型號： | INTELDX2 |
| 廠商： | Intel Corp. |
| 英文描述： | High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器) |
| 中文描述： | 高性能32位嵌入式處理器（高性能32位嵌入式處理器） |
| 文件頁數(shù)： | 26/48頁 |
| 文件大小： | 486K |
| 代理商： | INTELDX2 |
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Embedded IntelDX2 Processor
22
NUMERIC ERROR REPORTING
FERR#
O
The
Floating Point Error
pin is driven active when a floating point error occurs.
FERR# is similar to the ERROR# pin on the Intel387 Math CoProcessor.
FERR# is included for compatibility with systems using DOS type floating point
error reporting. FERR# will not go active if FP errors are masked in FPU register.
FERR# is active LOW, and is not floated during bus hold.
When the
Ignore Numeric Error
pin is asserted the processor will ignore a
numeric error and continue executing non-control floating point instructions, but
FERR# will still be activated by the processor. When IGNNE# is de-asserted the
processor will freeze on a non-control floating point instruction, if a previous
floating point instruction caused an error. IGNNE# has no effect when the NE bit
in control register 0 is set. IGNNE# is active LOW and is provided with a small
internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t
20
and t
21
must be met to ensure recognition on any specific clock.
IGNNE#
I
RESERVED PINS
RESERVED#
I
Reserved
is reserved for future use. This pin MUST be connected to an external
pull-up resistor circuit. The recommended resistor value is 10 kOhms. The pull-up
resistor must be connected only to the RESERVED# pin.
Do not share this
resistor with other pins requiring pull-ups.
Table 8.
Embedded IntelDX2 Processor Pin Descriptions
(Sheet 7 of 7)
Symbol
Type
Name and Function
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