參數(shù)資料
型號： INTELDX2
廠商： Intel Corp.
英文描述： High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器)
中文描述： 高性能32位嵌入式處理器（高性能32位嵌入式處理器）
文件頁數(shù)： 20/48頁
文件大?。?/td> 486K
代理商： INTELDX2
Embedded IntelDX2 Processor
16
3.2
Pin Quick Reference
The following is a brief pin description. For detailed signal descriptions refer to Appendix A, “Signal Descrip-
tions,” in the Embedded Intel486 Processor Family Developer’s Manual,
order No. 273021.
Table 8.
Embedded IntelDX2 Processor Pin Descriptions
(Sheet 1 of 7)
Symbol
CLK
Type
I
Name and Function
Clock
provides the fundamental timing and internal operating frequency for the
embedded IntelDX2 processor. All external timing parameters are specified with
respect to the rising edge of CLK.
ADDRESS BUS
A31-A4
A3–A2
I/O
O
Address Lines
A31–A2, together with the byte enable signals, BE3#–BE0#,
define the physical area of memory or input/output space accessed. Address
lines A31–A4 are used to drive addresses into the embedded IntelDX2 processor
to perform cache line invalidation. Input signals must meet setup and hold times
t
22
and t
23
. A31–A2 are not driven during bus or address hold.
Byte Enable
signals indicate active bytes during read and write cycles. During
the first cycle of a cache fill, the external system should assume that all byte
enables are active. BE3#–BE0# are active LOW and are not driven during bus
hold.
BE3# applies to D31–D24
BE2# applies to D23–D16
BE1# applies to D15–D8
BE0# applies to D7–D0
BE3#
BE2#
BE1#
BE0#
O
O
O
O
DATA BUS
D31–D0
I/O
Data Lines.
D7–D0 define the least significant byte of the data bus; D31–D24
define the most significant byte of the data bus. These signals must meet setup
and hold times t
and t
for proper operation on reads. These pins are driven
during the second and subsequent clocks of write cycles.
DATA PARITY
DP3–DP0
I/O
There is one
Data Parity
pin for each byte of the data bus. Data parity is
generated on all write data cycles with the same timing as the data driven by the
embedded IntelDX2 processor. Even parity information must be driven back into
the processor on the data parity pins with the same timing as read information to
ensure that the correct parity check status is indicated by the embedded IntelDX2
processor. The signals read on these pins do not affect program execution.
Input signals must meet setup and hold times t
and t
. DP3–DP0 must be
connected to V
through a pull-up resistor in systems that do not use parity.
DP3–DP0 are active HIGH and are driven during the second and subsequent
clocks of write cycles.
Parity Status
is driven on the PCHK# pin the clock after ready for read
operations. The parity status is for data sampled at the end of the previous clock.
A parity error is indicated by PCHK# being LOW. Parity status is only checked for
enabled bytes as indicated by the byte enable and bus size signals. PCHK# is
valid only in the clock immediately after read data is returned to the processor. At
all other times PCHK# is inactive (HIGH). PCHK# is never floated.
PCHK#
O
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