
LPC Interface Bridge Registers (D31:F0)
8-40
82801AA and 82801AB Datasheet
8.5.3
DAT—Data Register
Memory Address
Default Value:
FEC0_0010h
00000000h
Attribute:
Size:
R/W
32 bits
This is a 32 bit register specifying the data to be read or written to the register pointed to by the
Index register. This register can be accessed in byte quantities.
8.5.4
ID—Identification Register
Index Offset:
Default Value:
00h
00000000h
Attribute:
Size:
R/W
32 bits
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is
derived from its I/O APIC ID. This register is reset to zero on power up reset
8.5.5
VER—Version Register
Index Offset:
Default Value:
01h
00170011h
Attribute:
Size:
RO
32 bits
Each I/O APIC contains a hardwired Version Register that identifies different implementation of
APIC and their versions. The maximum redirection entry information also is in this register, to let
software know how many interrupt are supported by this APIC.
Bit
Description
7:0
APIC Data.
This is an 32 bit register for the data to be read or written to the APIC indirect register
pointed to by the Index register.
Bit
Description
31:28
Reserved.
27:24
APIC ID.
Software must program this value before using the APIC.
23:0
Reserved.
Bit
Description
31:24
Reserved.
23:16
Maximum Redirection Entries.
This is the entry number (0 being the lowest entry) of the highest
entry in the redirection table. It is equal to the number of interrupt input pins minus one and is in the
range 0 through 239. This field is hardwired and is read-only. In the ICH this field is hardwired to 17h
to indicate 24 interrupts.
15
PRQ.
This bit is set to 1 to indicate that this version of the I/O APIC implements the IRQ Assertion
register and allows PCI devices to write to it to cause interrupts.
14 :8
Reserved.
7:0
Version.
This is a version number that identifies the implementation version. This field is hardwired
and is read only.