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參數(shù)資料
| 型號(hào)： | S1C88409D |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁(yè)數(shù)： | 96/250頁(yè) |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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S1C88409 TECHNICAL MANUAL
EPSON
175
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Touch Panel Controller)
ETPPD, ETPDR: Interrupt enable register
(00FF26HD6, D5)
Enables or disables the touch panel controller
interrupt generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
The ETPPD and ETPDR registers are the interrupt
enable registers corresponding to the pen-down
interrupt and conversion data update interrupt
factors, respectively. When the register is set to "1",
the interrupt is enabled, and when it is set to "0",
the interrupt is disabled.
At initial reset, the EPD and EDLP registers are set
to "0" (interrupt is disabled).
FTPPD, FTPDR: Interrupt factor flag
(00F2AHD6, D5)
Indicates the generation of touch panel controller
interrupt factor.
When "1" is read: Int. factor has generated
When "0" is read: Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FTPPD and FTPDR are the interrupt factor flags
corresponding to the pen-down interrupt and
conversion data update interrupt, respectively. They
are set to "1" when the corresponding factor occurs.
The pen-down interrupt factor occurs when a pen-
down status is detected during pen-down check.
The conversion data update interrupt factor occurs
when the coordinate values (result of arithmetic
mean) after A/D conversions are written to the
coordinate data registers.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion conditions are met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to reset the
interrupt flag (set the interrupt flag to a lower level
than the level indicated by the interrupt priority
registers, or execute the RETE instruction) and to
reset the interrupt factor flag. The interrupt factor
flag is reset to "0" by writing "1".
At initial reset, the FPD and FDLP flags are reset to
"0".
5.17.7 Programming notes
(1) The setting of the threshold value for drawing
speed judgment in the normal mode must meet
following conditions.
MVH
≥ MVMH ≥ MVML ≥ MVL
(2) Do not stop the clocks output from the OSC3
oscillation circuit and prescaler during coordi-
nate detection.
(3) Do not operate the A/D converter indepen-
dently while the touch panel controller is used.
(4) The waiting time to be set using the WAIT
register must be longer than 3 cycles of the
OSC1 clock.
16
× n/f > 3/fOSC1
(
f: Input clock frequency from the prescaler)
When the A/D converter reference voltage
control function is used (VRC = "1"), the time
set in the WAIT register also applies to the
reference voltage setup time. Therefore, design
the peripheral circuit taking the charge time
into consideration. If the reference voltage
(AVREF) cannot be set up within the time set in
the WAIT register, the reference voltage should
be switched on and off by software so that the
setup time is secured.
(5) The capacitors connected to Ch0 and Ch1 of the
touch panel controller (see Figure 5.17.2.1)
affect the pen-down judgement time. They
must be 1000 pF or less.
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