
S1C88409 TECHNICAL MANUAL
EPSON
29
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (I/O Memory Map)
Table 5.1.1(f) I/O Memory map (00FF30H–00FF37H)
Address
Function
R/W
Init
0
1
Comment
Name
Bit
00FF30
16-bit PTM 8-/16-bit mode selection
–
16-bit PTM0 clock output control
16-bit PTM0 RUN/STOP control
16-bit PTM0 preset
16-bit PTM0 input clock selection
R/W
–
R/W
W
R/W
0
–
0
8-bit
× 2
–
Off
Stop
Invalid
Internal clock
16-bit
–
On
Run
Preset
External clock
"0" when being read
MODE16
–
PTOUT0
PTRUN0
PSET0
CKSEL0
D7
D6
D5
D4
D3
D2
D1
D0
00FF31
–
16-bit PTM1 clock output control
16-bit PTM1 RUN/STOP control
16-bit PTM1 preset
16-bit PTM1 input clock selection
–
R/W
W
R/W
–
0
–
Off
Stop
Invalid
Internal clock
–
On
Run
Preset
External clock
"0" when being read
–
PTOUT1
PTRUN1
PSET1
CKSEL1
D7
D6
D5
D4
D3
D2
D1
D0
00FF32
16-bit programmable timer 0
reload data register
R/W
1
Low-order 8 bits data
in 16-bit mode
RDR07
RDR06
RDR05
RDR04
RDR03
RDR02
RDR01
RDR00
D7
D6
D5
D4
D3
D2
D1
D0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
00FF33
16-bit programmable timer 1
reload data register
R/W
1
High-order 8 bits data
in 16-bit mode
RDR17
RDR16
RDR15
RDR14
RDR13
RDR12
RDR11
RDR10
D7
D6
D5
D4
D3
D2
D1
D0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
00FF34
16-bit programmable timer 0
compare data register
R/W
0
Low-order 8 bits data
in 16-bit mode
CDR07
CDR06
CDR05
CDR04
CDR03
CDR02
CDR01
CDR00
D7
D6
D5
D4
D3
D2
D1
D0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
00FF35
16-bit programmable timer 1
compare data register
R/W
0
High-order 8 bits data
in 16-bit mode
CDR17
CDR16
CDR15
CDR14
CDR13
CDR12
CDR11
CDR10
D7
D6
D5
D4
D3
D2
D1
D0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
00FF36
16-bit programmable timer 0
data register
R
1
Low-order 8 bits data
in 16-bit mode
PTM07
PTM06
PTM05
PTM04
PTM03
PTM02
PTM01
PTM00
D7
D6
D5
D4
D3
D2
D1
D0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
00FF37
16-bit programmable timer 1
data register
R
1
High-order 8 bits data
in 16-bit mode
PTM17
PTM16
PTM15
PTM14
PTM13
PTM12
PTM11
PTM10
D7
D6
D5
D4
D3
D2
D1
D0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)