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參數(shù)資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 52/250頁 |
| 文件大小： | 1877K |
| 代理商： | S1C88409D |
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S1C88409 TECHNICAL MANUAL
EPSON
135
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
5.14.5 Control procedure to transmit/receive
This section explains the control registers used to
transmit and receive.
Shift register and receive data buffer
The serial interface is equipped with a shift
register for serial/parallel conversion.
Transmit data written in the transmit/receive data
register TRXD is converted to serial data through
the shift register and is output from the SOUT
terminal.
Besides the shift register, the receiver is equipped
with a receive data buffer.
At the time of receiving, data input from the SIN
terminal is converted to parallel data through the
shift register and loaded into the receive data buffer.
However, the buffering function cannot be used in
the clock synchronous mode. Therefore, it is
necessary to read the received data before starting
the next data receiving.
Transmission enable register
and transmission control bit
The transmission enable register TXEN and the
transmission control bit TXTRG are used to control
transmissions.
The transmission enable register TXEN enables and
disables transmission. Writing "1" to this register
enables transmission. In this status, clock input of the
shift register is authorized, and the transmitter shifts
into transmit standby status. In the clock synchro-
nous mode, the synchronous clock input and output
of the SCLK terminal is authorized, too.
The transmission control bit TXTRG is used as a
trigger for starting transmissions.
To start a transmission, write "1" to TXTRG after a
preparation to transmit has been completed by
writing transmit data to the transmit/receive data
register TRXD.
When the transmission is completed, an interrupt
is generated when the interrupt has been enabled.
After the interrupt is generated, the next transmit
data can be written.
TXTRG can also be read as a status. It goes "1"
during transmission and goes "0" during standby
(stopped) status.
Refer to Section 5.14.9, "Timing charts", for timing
of transmission.
Note: Do not set interface conditions, such as
transfer mode, when the TXEN register is
"1" (transmission authorize status). Setting
except for transmission control must be
done after writing "0" to the TXEN register.
Receiving enable register
and receiving control bit
The receiving enable register RXEN and receiving
control bit RXTRG are used to control receiving.
The receiving enable register RXEN enables and
disables receiving. Writing "1" to this register
enables receiving. In this status, clock input of the
shift register is authorized, and the receiver shifts
into receive standby status. In the clock synchro-
nous mode, the synchronous clock input and
output of the SCLK terminal is authorized, too.
When serial data is sent from the transmitter in
this status, the data is loaded in the shift register.
When receiving has completed, an interrupt is
generated when the interrupt has been enabled.
The operation of the receiving control bit RXTRG
is slightly different depending on whether the
clock synchronous mode or the asynchronous
mode is being used.
In the clock synchronous mode, RXTRG is used as
a trigger to start receiving.
When received data has been read and the prepa-
ration for the next data receiving is completed,
write "1" in RXTRG to start receiving. (In the slave
mode, the SRDY signal goes "0" when "1" is written
to RXTRG.)
In the asynchronous mode, RXTRG is used to
prepare for the next data receiving. After reading
the received data from the receive data buffer,
write "1" in RXTRG to signify that the receive data
buffer is empty. If "1" is not written in RXTRG, the
overrun error flag OER will be set to "1" when the
next receiving is completed. (An overrun error will
be generated when the next receiving is completed
between reading the previously received data and
the writing of "1" to RXTRG.)
RXTRG can also be read as a status. It goes "1"
during receiving and goes "0" during standby
(stopped) status. This function is the same in either
the clock synchronous mode or the asynchronous
mode.
Refer to Section 5.14.9, "Timing charts", for timing
of receiving.
Note: Do not set interface conditions, such as
transfer mode, when the RXEN register is
"1" (receiving authorize status). Setting
except for receiving control must be done
after writing "0" to the RXEN register.
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