- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98069 > S1C88409D 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁(yè)數(shù)： | 116/250頁(yè) |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)當(dāng)前第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)
192
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and Standby Mode)
5.20.4 Interrupt factor flag
The interrupt factor flag is set to "1" when the
corresponding interrupt factor generates.
By reading the interrupt factor flag, it is possible to
confirm the interrupt factor that has been gener-
ated.
Interrupt factor flag that has been set to "1" is reset
to "0" by writing "1".
At initial reset, all the interrupt factor flags are
reset to "0".
Note: When the RETE instruction is executed
without resetting the interrupt factor flag
after an interrupt has been generated, the
same interrupt is generated again. There-
fore, the interrupt factor flag must be reset
(writing "1") in the interrupt handler routine.
5.20.5 Interrupt enable register
The interrupt enable registers corresponding to all
interrupt factor flags are provided to enable/
disable the interrupt requests to the CPU.
When "1" is written to the interrupt enable register,
the interrupt request is enabled and when "0" is
written, it is disabled. This register can also be
read, thus making it possible to confirm the setting
status.
At initial reset, all the interrupt enable registers are
set to "0" and all the interrupts except for NMI are
disabled.
5.20.6 Interrupt priority register and
interrupt priority level
Each interrupt system provides the interrupt
priority register shown in Table 5.20.3.1. By using
the interrupt priority register, the priority of each
interrupt can be changed so that the CPU can
process interrupt in order of priority. Conse-
quently, it is possible to make a multiple interrupt
system that meets the demand of the application.
The priority level of each interrupt system can be
optionally set to four levels (0 to 3) by the interrupt
priority register. However, when two or more
systems are set to the same priority level, they are
processed according to the default priority level.
Table 5.20.6.1 Setting of interrupt priority level
P 1
1
0
Interrupt priority level
Level 3
Level 2
Level 1
Level 0
P 0
1
0
1
0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
**
At initial reset, all the interrupt priority registers
are set to "0" and all interrupts are set to level 0.
Furthermore, the priorities inside of each system
have been previously decided and they cannot be
changed.
The CPU can mask each interrupt by setting the
interrupt flags (I0 and I1). The relation between the
interrupt priority level of each system and inter-
rupt flags is shown in Table 5.20.6.2. The CPU
accepts only interrupts set in a higher level than
the interrupt flag setting.
The priority level of NMI (watchdog timer) is set
in level 4, so it is always accepted regardless of the
interrupt flag setting.
Table 5.20.6.2 Interrupt mask setting for CPU
I1
1
0
Acceptable interrupt
Level 4 (NMI)
Level 4, Level 3 (IRQ3)
Level 4, Level 3, Level 2 (IRQ2)
Level 4, Level 3, Level 2, Level 1 (IRQ1)
I0
1
0
1
0
After an interrupt is accepted, the interrupt flags
are changed to the same level of the interrupt
accepted as shown in Table 5.20.6.3 in order to
mask interrupt requests with the same priority
level or less. However, it is set to level 3 after an
NMI is accepted.
Table 5.20.6.3 Interrupt flags after
acceptance of interrupt
I1
1
0
Accepted interrupt priority level
Level 4
Level 3
Level 2
Level 1
I0
1
0
1
(NMI)
(IRQ3)
(IRQ2)
(IRQ1)
The interrupt flags changed are returned to the
previous value at return from the interrupt
handler routine.
Multiple interrupts up to 3 levels can be controlled
by only setting the interrupt priority registers.
Multiple interrupts exceeding 3 levels can be realized
by rewriting the interrupt flags and interrupt enable
register in the interrupt handler routine.
Note: Be aware if the interrupt flags are rewritten
(set to lower priority) prior to resetting the
interrupt factor flag after an interrupt is
generated, the same interrupt will be
generated again.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C88816D | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC164 |
| S1C88832F0A0100 | MICROCONTROLLER, PQFP128 |
| S1C88848D0A0100 | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192 |
| S1C8F360F | 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176 |
| S1D13305F00B | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C88649 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88650 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88655 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88816 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88848 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。