
22
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 4: INITIAL RESET
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is
to input a LOW level simultaneously to the input
ports (K00–K03) selected by mask option.
Since there is a built-in time authorize circuit, be
sure to maintain the designated input port termi-
nal at LOW level for two seconds (when the
oscillation frequency is fOSC1 = 32.768 kHz) or
more to perform the initial reset by means of this
function.
However, the time authorize circuit is bypassed
during the SLEEP (standby) status and oscillation
stabilization waiting period, and initial reset is
executed immediately after the simultaneous LOW
level input to the designated input ports.
The combination of input ports (K00–K03) that can
be selected by mask option are as follows:
(1) Not use
(2) K00 & K01
(3) K00 & K01 & K02
(4) K00 & K01 & K02 & K03
For instance, let's say that mask option (4) "K00 &
K01 & K02 & K03" is selected.
When the input level at input ports K00–K03 is
simultaneously LOW, initial reset will take place.
When using this function, make sure that the
designated input ports do not simultaneously
switch to LOW level while the system is in normal
operation.
4.2 Initial Reset Sequence
After cancellation of the LOW level input to the
RESET terminal, when the power is turned on, the
start-up of the CPU is held back until the oscilla-
tion stabilization waiting time (8,192/fOSC1 sec.)
has elapsed.
Figure 4.2.1 shows the operating sequence follow-
ing initial reset release.
Also, when using the initial reset by simultaneous
LOW level input into the input port, you should be
careful of the following points.
(1) During SLEEP status, since the time authoriza-
tion circuit is bypassed, an initial reset is
triggered immediately after a LOW level
simultaneous input value. In this case, the CPU
starts after waiting the oscillation stabilization
time, following cancellation of the LOW level
simultaneous input.
(2) Other than during SLEEP status, an initial reset
will be triggered 1–2 seconds after a LOW level
simultaneous input. In this case, since a reset
differential pulse (64/fOSC1 sec.) is generated
inside the S1C88409, the CPU will start even if
the LOW level simultaneous input status is not
canceled.
PC
00-0000
Dummy
VECL
fOSC1
RESET
Internal initial reset
Internal address bus
Internal data bus
Internal read signal
8192/fOSC1 [sec]
Oscillation stable waiting time
Dummy cycle
Reset exception processing
Fig. 4.2.1 Initial reset sequence