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參數(shù)資料
| 型號(hào)： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 44/250頁 |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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128
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer)
In the case of STOP status, the counter maintains
the preset data.
No operation results when "0" is written.
This bit is valid only for writing, and it is always
"0" during reading.
PRUN: RUN/STOP control register
(00FF38HD0)
Controls the RUN/STOP of the counter.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The counter starts down-counting by writing "1" to
the PRUN register and stops by writing "0".
In STOP status, the counter data is maintained
until it is preset or the counter restarts. When
STOP status changes to RUN status, the counter
resumes counting from the data maintained.
At initial reset, the PRUN register is set to "0"
(STOP).
PTOUT: Clock output control register
(00FF38HD2)
Controls the clock output to the serial interface.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
The PTOUT register is the output control register.
When "1" is written to this register, the clock
(underflow
1/2) that is generated by the 8-bit
programmable timer is output to the serial inter-
face.
When "0" is written, the clock is not output to the
serial interface.
At initial reset, the PTOUT register is set to "0"
(OFF).
PTM20, PTM21: Interrupt priority register
(00FF21HD6, D7)
Sets the priority level of the 8-bit programmable
timer interrupt.
Table 5.13.6.2 shows the interrupt priority level
which can be set by this register.
Table 5.13.6.2 Interrupt priority level settings
PTM21
1
0
Interrupt priority level
Level 3
Level 2
Level 1
Level 0
PTM20
1
0
1
0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
At initial reset, the PTM2 register is set to "0" (level 0).
ETU2: Underflow interrupt enable register
(00FF24HD7)
Enables or disables the underflow interrupt
generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
The ETU2 register is the interrupt enable register
corresponding to the interrupt factor of the 8-bit
programmable timer.
Interrupt in which the ETU2 register is set to "1" is
enabled, and the others in which the ETU2 register
is set to "0" are disabled.
At initial reset, the ETU2 register is set to "0"
(interrupt is disabled).
FTU2: Underflow interrupt factor flag
(00FF28HD7)
Indicates the generation of underflow interrupt
factor.
When "1" is read: Int. factor has generated
When "0" is read: Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FTU2 is the interrupt factor flag corresponding to
the 8-bit programmable timer interrupt, and is set
to "1" due to the counter underflow.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
At initial reset, the FTU2 flag is reset to "0".
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