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參數(shù)資料
| 型號(hào)： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁(yè)數(shù)： | 21/250頁(yè) |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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S1C88409 TECHNICAL MANUAL
EPSON
107
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
TMD0–TMD7: Clock timer data (00FF51H)
The clock timer data (128 Hz–1 Hz) can be read.
Correspondence between TMD bit and frequency
is as follows:
TMD0: 128 Hz
TMD4: 8 Hz
TMD1: 64 Hz
TMD5: 4 Hz
TMD2: 32 Hz
TMD6: 2 Hz
TMD3: 16 Hz
TMD7: 1 Hz
Since TMD is read only, the writing operation is
invalid.
At initial reset, the timer data is set to "00H".
TMMD0–TMMD6: 60-second counter data
(00FF52HD0–D6)
The 60-second counter data can be read.
Correspondence between TMMD bit and data is as
follows:
TMMD6–TMMD4:
10 sec BCD data
TMMD3–TMMD0:
1 sec BCD data
When data is written to the TMMD register, it is
preset to the 60-second counter. At the same time,
the timer for 128 Hz to 1 Hz is also reset.
The counter is preset only when data is written to
the TMMD register. The register does not maintain
the preset data and returns to 0-second when the
counter overflows.
To prevent the counter from abnormal operation,
do not preset data without a range of 0 to 59
(BCD).
At initial reset, the counter data is set to "0".
TMRST: Clock timer reset (00FF50HD1)
Resets the clock timer.
When "1" is written: Clock timer reset
When "0" is written: No operation
Reading: Always "0"
The clock timer TMD and the 60S counter TMMD
are reset by writing "1" to TMRST. When the clock
timer is reset in RUN status, it restarts immedi-
ately after resetting. In the case of STOP status, the
reset data "00H" is maintained.
No operation results when "0" is written to TMRST.
TMRST is write only, and so it is always "0" at
reading.
TMRUN: Clock timer RUN/STOP control register
(00FF50HD0)
Controls RUN/STOP of the clock timer.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The clock timer starts counting by writing "1" to
the TMRUN register and stops by writing "0".
In STOP status, the count data is maintained until
the timer is reset or is set in the next RUN status.
Also, when STOP status changes to RUN status,
the data that was maintained can be used for
resuming the count.
At initial reset, the TMRUN register is set to "0"
(STOP).
PCTM0, PCTM1: Clock timer interrupt priority
register (00FF21HD2, D3)
Sets the priority level of the clock timer interrupt.
The PCTM register is the interrupt priority register
corresponding to the clock timer interrupt.
Table 5.11.3.2 shows the interrupt priority level
which can be set by this register.
Table 5.11.3.2 Interrupt priority level settings
PCTM1
1
0
Interrupt priority level
Level 3
Level 2
Level 1
Level 0
PCTM0
1
0
1
0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
At initial reset, the PCTM register is set to "0"
(level 0).
ECTM32: Clock timer 32 Hz interrupt enable
register (00FF25HD3)
ECTM8: Clock timer 8 Hz interrupt enable
register (00FF25HD4)
ECTM2: Clock timer 2 Hz interrupt enable
register (00FF25HD5)
ECTM1: Clock timer 1 Hz interrupt enable
register (00FF25HD6)
ET60S: Clock timer 60S interrupt enable
register (00FF25HD7)
Enables or disables the interrupt generation to the
CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
ECTM32, ECTM8, ECTM2, ECTM1 and ET60S are
the interrupt enable registers corresponding to 32
Hz, 8 Hz, 2 Hz, 1 Hz and 60S interrupt factors.
Interrupt of the frequency in which the ECTM
register is set to "1" is enabled, and the others in
which the ECTM register is set to "0" are disabled.
At initial reset, the interrupt enable registers are all
set to "0" (interrupt is disabled).
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