
S1C88409 TECHNICAL MANUAL
EPSON
141
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
5.14.9 Timing charts
The following shows the transmit/receive timing
chart for each transfer mode.
Clock synchronous master mode
This mode uses a clock generated by dividing the
8-bit programmable timer output in 1/16 as the
synchronous clock SCLK. (See Figure 5.14.4.1.)
(1) Transmission timing in clock synchronous master
mode
Figure 5.14.9.1 shows the transmission timing
in clock synchronous master mode.
By writing "1" to the TXTRG bit, the synchro-
nous clock is output from the SCLK terminal.
Each bit of transmission data is output from the
SOUT terminal at the falling edge of the
synchronous clock. When the last bit is output,
a transmit completion interrupt is generated at
the rising edge of the synchronous clock.
Note: Do not write data to TXTRG, RXTRG and
the TRXD register during transmission
(while reading of TXTRG is "1").
(2) Receiving timing in clock synchronous master
mode
Figure 5.14.9.2 shows the receiving timing in
clock synchronous master mode.
By writing "1" to the RXTRG bit, the synchro-
nous clock is output from the SCLK terminal.
The status of the SIN terminal is input at each
rising edge of the synchronous clock. When the
last bit is input, a receive completion interrupt
is generated simultaneously. After the interrupt
is generated, the received data can be read
from the TRXD register.
Note: Do not write data to TXTRG, RXTRG and
the TRXD register during receiving (while
reading of RXTRG is "1").
Fig. 5.14.9.1 Transmission timing (clock synchronous master mode)
Fig. 5.14.9.2 Receiving timing (clock synchronous master mode)
TXEN
TXTRG (WR)
SCLK
SOUT
TXTRG (RD)
Transmit completion
interrupt generation
D0
D1
D2
D3
D4
D5
D6
D7
RXEN
RXTRG (WR)
SCLK
SIN
TRXD (RD)
RXTRG (RD)
Receive completion
interrupt generation
Received data
D0
D1
D2
D3
D4
D5
D6
D7