
S1C88409 TECHNICAL MANUAL
EPSON
213
CHAPTER 8: ELECTRICAL CHARACTERISTICS
8.5.4 LCD controller
Item
XSCL H-level pulse width (B&W, 4 bits)
XSCL H-level pulse width (gray, 4 bits)
LP falling edge to XSCL rising edge
LCD data setup time
LCD data hold time
YD H-level pulse width
LP H-level pulse width
YD setup time
YD hold time
FR change from LP falling edge
XSCL H-level pulse width (B&W, 4 bits)
XSCL H-level pulse width (gray, 4 bits)
LP falling edge to XSCL rising edge
LCD data setup time
LCD data hold time
YD H-level pulse width
LP H-level pulse width
YD setup time
YD hold time
FR change from LP falling edge
XSCL H-level pulse width (B&W, 4 bits)
XSCL H-level pulse width (gray, 4 bits)
LP falling edge to XSCL rising edge
LCD data setup time
LCD data hold time
YD H-level pulse width
LP H-level pulse width
YD setup time
YD hold time
FR change from LP falling edge
XSCL H-level pulse width (B&W, 4 bits)
XSCL H-level pulse width (gray, 4 bits)
LP falling edge to XSCL rising edge
LCD data setup time
LCD data hold time
YD H-level pulse width
LP H-level pulse width
YD setup time
YD hold time
FR change from LP falling edge
Unless otherwise specified:
VDD=5.5 V, VSS=0 V, fOSC1=32.768 kHz, fOSC3=2.0 MHz, Ta=-20 to 70
°C, CL=100 pF,
VIH=0.8VDD, VIL=0.2VDD, VOH=0.8VDD, VOL=0.2VDD
Symbol
tHXS(1)
tHXS(2)
tLPXS
tDS
tDH
tHYD
tHLP
tYDLPL
tLPYD
tLPFR
tHXS(1)
tHXS(2)
tLPXS
tDS
tDH
tHYD
tHLP
tYDLPL
tLPYD
tLPFR
tHXS(1)
tHXS(2)
tLPXS
tDS
tDH
tHYD
tHLP
tYDLPL
tLPYD
tLPFR
tHXS(1)
tHXS(2)
tLPXS
tDS
tDH
tHYD
tHLP
tYDLPL
tLPYD
tLPFR
Unit
ns
s
ns
s
ns
s
ns
s
ns
Note
Max.
–
300
–
200
–
100
–
100
Typ.
–
Min.
tc-360
tc-tl-360
6*
tc-360
tc(fOSC1)-3
tl(fOSC1)-1.5
th(fOSC1)-1.5
-300
tc-180
tc-tl-180
6*
tc-180
tc(fOSC1)-3
tl(fOSC1)-1.5
th(fOSC1)-1.5
-200
tc-90
tc-tl-90
6*
tc-90
tc(fOSC1)-3
tl(fOSC1)-1.5
th(fOSC1)-1.5
-100
tc-90
tc-tl-90
6*
tc-90
tc(fOSC1)-3
tl(fOSC1)-1.5
th(fOSC1)-1.5
-100
tc=OSC3 clock cycle time, th=OSC3 clock H pulse width, tl=OSC3 clock L pulse width, tc(fOSC1)=OSC1 clock cycle time
th(fOSC1)=OSC1 clock H pulse width, tl(fOSC1)=OSC1 clock L pulse width
Condition
VDD=1.8 to 5.5 V
VD1=1.6 V
VDD=2.6 to 5.5 V
VD1=2.4 V
VDD=3.5 to 5.5 V
VD1=3.2 V
VDD=4.5 to 5.5 V
VD1=4.2 V
FR
YD
LP
XSCL
SD0–SD3
tDS
tHYD
tDH
tHLP
tLPFR
tLPYD
tHXS
tLPXS
tYDLPL