
S1C88409 TECHNICAL MANUAL
EPSON
127
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (8-bit Programmable Timer)
Table 5.13.6.1(b) 8-bit programmable timer control bits
Address
Function
R/W
Init
0
1
Comment
Name
Bit
00FF38
–
8-bit programmable timer clock output control
8-bit programmable timer preset
8-bit programmable timer RUN/STOP control
–
R/W
W
R/W
–
0
–
0
–
Off
Invalid
Stop
–
On
Preset
Run
"0" when being read
–
PTOUT
PSET
PRUN
D7
D6
D5
D4
D3
D2
D1
D0
00FF39
8-bit programmable timer
reload data register
R/W
1
RLD7
RLD6
RLD5
RLD4
RLD3
RLD2
RLD1
RLD0
D7
D6
D5
D4
D3
D2
D1
D0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
00FF3A
8-bit programmable timer
data register
R
1
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
D7
D6
D5
D4
D3
D2
D1
D0
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
PST20–PST22: 8-bit programmable timer
division ratio selection register (00FF11HD0–D2)
Selects the clock for the 8-bit programmable timer.
It can be selected from 8 types of division ratio
shown in Table 5.13.6.1(a).
This register can also be read.
At initial reset, the PST2 register is set to "0"
(fOSC3/2).
PRPRT2: 8-bit programmable timer
clock control register (00FF11HD3)
Controls the clock supply of the 8-bit program-
mable timer.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
By writing "1" to the PRPRT2 register, the clock
that is selected with the PST2 register is output to
the 8-bit programmable timer. However, the OSC3
oscillation circuit must be used.
When "0" is written, the clock is not output.
At initial reset, the PRPRT2 register is set to "0"
(OFF).
RLD0–RLD7: Reload data register
(00FF39H)
Sets the initial value for the counter.
The counter loads the reload data set in this
register and counts using it as the initial value.
The reload data set in this register is loaded into
the counter when "1" is written to PSET, or when a
counter underflow occurs.
This register can be read.
At initial reset, the RLD register is set to "FFH".
PTD0–PTD7: Counter data (00FF3AH)
The counter data of the 8-bit programmable timer
can be read.
PTD is a buffer to maintain the count data during
reading, and the data can be read in optional
timing.
At initial reset, PTD is set to "FFH".
PSET: Preset (00FF38HD1 )
Presets the reload data to the counter.
When "1" is written: Preset
When "0" is written: Invalid
Reading: Always "0"
Writing "1" to PSET presets the reload data in the
RLD register to the counter. When the counter is in
RUN status, the counter restarts immediately after
presetting.