
S1C88409 TECHNICAL MANUAL
EPSON
19
CHAPTER 3: CPU AND MEMORY
Output
port
CE
signal
R30
R31
R32
CE0
CE1
CE2
64K
4M
(max.)
4M
(min.)
Single
chip
Bus mode
Fig. 3.6.4.1 Correspondence between CE signals and
output ports
The memory size assigned to three chip enable
(CE) signals is determined by the bus mode
setting.
In the expanded 64K mode, four decoder outputs
can be selected by software according to the
memory expanded.
Table 3.6.4.1 shows the addressable ranges which
are assigned to the chip enable (CE) signal in each
mode.
Table 3.6.4.1 CE0–CE2 address settings
CE
signal
CE0
CE1
CE2
Addressing range (selected with software)
8KB
008000H–009FFFH
00A000H–00BFFFH
00C000H–00DFFFH
16KB
007000H–00AFFFH
00B000H–00EFFFH
–
32KB
008000H–00EFFFH
–
(1) Expanded 64K mode + MCU mode
CE
signal
CE0
CE1
CE2
Addressing range (selected with software)
8KB
000000H–001FFFH
002000H–003FFFH
004000H–005FFFH
16KB
000000H–003FFFH
004000H–007FFFH
008000H–00BFFFH
32KB
000000H–007FFFH
008000H–00EFFFH
–
64KB
000000H–00EFFFH
–
(2) Expanded 64K mode + MPU mode
CE
signal
CE0
CE1
CE2
Addressing range (selected with software)
MCU mode
C00000H–FFFFFFH
400000H–7FFFFFH
800000H–BFFFFFH
MPU mode
000000H–00EFFFH, 010000H–3FFFFFH
400000H–7FFFFFH
800000H–BFFFFFH
(3) Expanded 4M minimum/maximum mode
When the internal memory area is accessed, the CE
signal is not output. Be aware that the part has
been irregular setting.
External devices can be allocated to an area
selected by an optional chip enable signal. It is not
necessary to continue from a lower address of the
memory space.
The chip enable signal is output only when the
external memory area is being accessed. It is not
output when the internal memory is accessed.
Furthermore, when the CPU is in standby status
(HALT, SLEEP), all the CE signals go HIGH. It
prohibits external memory access and gets the
CPU into power save mode.
Refer to Section 3.6.5, "WAIT control", for the
signal output timing.