
S1C88409 TECHNICAL MANUAL
EPSON
157
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
5.16.3 I/O memory of SVD circuit
Table 5.16.3.1 shows the control bits for the SVD circuit.
Table 5.16.3.1 SVD circuit control bits
Address
Function
R/W
Init
0
1
Comment
Name
Bit
00FF56
–
SVD criteria voltage setting
SVD data
SVD On/Off control
–
R/W
R
R/W
–
0
–
Normal
Off
–
Low
On
"0" when being read
–
SVD1
SVD0
SVDDT
SCDON
D7
D6
D5
D4
D3
D2
D1
D0
SVD1
1
0
SVD0
×
1
0
Voltage (V)
3.4 V
2.8 V
1.9 V
SVD0, SVD1: SVD criteria voltage setting
register (FF56HD2, D3)
Criteria voltage for SVD is set as shown in Table
5.16.3.1.
At initial reset, this SVD register is set to "0" (1.9 V).
SVDON: SVD control (ON/OFF) register
(FF56HD0)
Turns the SVD circuit ON and OFF.
When "1" is written: SVD circuit ON
When "0" is written: SVD circuit OFF
Reading: Valid
When the SVDON register is set to "1", a source
voltage detection is executed by the SVD circuit.
As soon as SVDON is reset to "0", the result is
loaded to the SVDDT latch. To obtain a stable
detection result, the SVD circuit must be ON for at
least l00 sec.
At initial reset, this SVD register is set to "0" (Off).
SVDDT: SVD data (FF56HD1)
This is the result of supply voltage detection.
When "0" is read: Supply voltage (VDD–VSS)
≥ Criteria voltage
When "1" is read: Supply voltage (VDD–VSS)
< Criteria voltage
Writing: Invalid
The result of supply voltage detection at time of
SVDON is set to "0" can be read from this latch.
At initial reset, SVDDT is set to "0" (Normal).
5.16.4 Programming notes
(1) To obtain a stable detection result, the SVD
circuit must be ON for at least l00 sec. So, to
obtain the SVD detection result, follow the
programming sequence below.
1. Set SVDON to "1"
2. Maintain for 100 sec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD operation increases current consump-
tion, so turn the SVD circuit off when voltage
detection is unnecessary or executing the SLP
instruction.