參數(shù)資料
型號(hào)： S1C88409D
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108
封裝： DIE-108
文件頁(yè)數(shù)： 34/250頁(yè)
文件大?。?/td> 1877K
代理商： S1C88409D
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S1C88409 TECHNICAL MANUAL
EPSON
119
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer)
RDR00–RDR07: Timer 0 reload data register
(00FF32H)
RDR10–RDR17: Timer 1 reload data register
(00FF33H)
Sets the initial value for the counter of each timer.
Each counter loads the reload data set in this
register and counts using it as the initial value.
The reload data set in this register is loaded into
the counter when "1" is written to PSET0 or PSET1,
or when a counter underflow occurs.
This register can be read.
At initial reset, the RDR register is set to "FFH".
CDR00–CDR07: Timer 0 compare data register
(00FF34H)
CDR10–CDR17: Timer 1 compare data register
(00FF35H)
Sets the compare data for each timer.
The timer compares the data set in this register
with the corresponding counter data, and outputs
the compare match signals when they are the
same. The compare match signal controls the
interrupt and the TOUT output waveform.
This register can be read.
At initial reset, the CDR register is set to "00H".
PTM00–PTM07: Timer 0 counter data
(00FF36H)
PTM10–PTM17: Timer 1 counter data
(00FF37H)
The counter data of each timer can be read.
Data can be read at any given time. However, in
the 16-bit mode, reading PTM0 does not latch the
timer 1 counter data in PTM1. To avoid generating
a borrow from timer 0 to timer 1, read the counter
data after stopping the timer by writing "0" to
PTRUN0.
PTM0 and PTM1 can only be read, so writing
operation is invalid.
At initial reset, PTM is set to "FFH".
PSET0: Timer 0 preset
(00FF30HD1)
PSET1: Timer 1 preset
(00FF31HD1)
Presets the reload data to the counter.
When "1" is written: Preset
When "0" is written: Invalid
Reading: Always "0"
Writing "1" to PSET0 presets the reload data in the
RDR0 register to the counter of Timer 0. When the
counter of Timer 0 is in RUN status, the counter
restarts immediately after presetting.
In the case of STOP status, the counter maintains
the preset data.
No operation results when "0" is written.
Same as above, PSET1 presets the reload data in
the RDR1 register to the counter of Timer 1.
In the 16-bit mode, writing "1" to PSET1 is invalid
because 16-bit data is preset by PSET0 only.
This bit is only for writing, and it is always "0"
during reading.
PTRUN0: Timer 0 RUN/STOP control register
(00FF30HD2)
PTRUN1: Timer 1 RUN/STOP control register
(00FF31HD2)
Controls the RUN/STOP of the counter.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
The counter of Timer 0 starts down-counting by
writing "1" to the PTRUN0 register and stops by
writing "0".
In STOP status, the counter data is maintained
until it is preset or the counter restarts. When
STOP status changes to RUN status, the counter
resumes counting from the data maintained.
Same as above, the PTRUN1 register controls the
counter of Timer 1.
In the 16-bit mode, both channels are controlled
with the PTRUN0 register, and the PTRUN1
register is fixed at "0".
At initial reset, the PTRUN register is set to "0"
(STOP).
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