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參數(shù)資料
| 型號： | S1C88409D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108 |
| 封裝： | DIE-108 |
| 文件頁數(shù)： | 125/250頁 |
| 文件大?。?/td> | 1877K |
| 代理商： | S1C88409D |
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200
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 6: SUMMARY OF NOTES
Serial interface
(1) Setting of the serial interface mode must be
done in the transmission/receiving disabling
status (TXEN = RXEN = "0").
(2) Do not perform double trigger (writing "1") to
TXTRG (RXTRG) during transmission (receiv-
ing). Furthermore, do not execute the SLP
instruction. (When executing the SLP instruc-
tion, set TXEN and RXEN to "0".)
(3) Transmission and receiving cannot be done
simultaneously in the clock synchronous mode
because the clock line (SCLK) is shared with
transmit and receive operation. Therefore, do
not write "1" to RXTRG (TXTRG) when TXTRG
(RXTRG) is "1".
(4) When a parity error or a framing error occurs,
both the receive error interrupt factor flag
FSERR and the receive completion interrupt
factor flag FSRX are simultaneously set to "1".
However, since the receive error interrupt has
priority over the receive completion interrupt,
the receive error interrupt process is executed
first. Therefore, it is necessary to reset the FSRX
flag in the receive error handling routine.
When a receive error interrupt occurs due to an
overrun, receive completion interrupt does not
occur.
Sound generator
(1) Since the BZ signal is generated asynchro-
nously from the register BZON, when the
signal is turned ON or OFF by the register
setting, a hazard of a 1/2 cycle or less is
generated.
(2) The SLP instruction has executed when the BZ
signal is in the enable status (BZON = "1" or
BZSHT = "1"), an unstable clock is output from
the R42 output port terminal at the time of
return from the SLEEP status. Consequently,
when shifting to the SLEEP status, you should
set the BZ signal to the disable status (BZON =
BZSHT = "0") prior to executing the SLP
instruction.
(3) The one-shot output is only valid when the
normal buzzer output is OFF (BZON = "0")
status. The trigger is invalid during ON (BZON
= "1") status.
SVD circuit
(1) To obtain a stable detection result, the SVD
circuit must be ON for at least l00 sec. So, to
obtain the SVD detection result, follow the
programming sequence below.
1. Set SVDON to "1"
2. Maintain for 100 sec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD operation increases current consump-
tion, so turn the SVD circuit off when voltage
detection is unnecessary or executing the SLP
instruction.
Touch panel controller
(1) The setting of the threshold value for drawing
speed judgment in the normal mode must meet
following conditions.
MVH
≥ MVMH ≥ MVML ≥ MVL
(2) Do not stop the clocks output from the OSC3
oscillation circuit and prescaler during coordi-
nate detection.
(3) Do not operate the A/D converter indepen-
dently while the touch panel controller is used.
(4) The waiting time to be set using the WAIT
register must be longer than 3 cycles of the
OSC1 clock.
16
× n/f > 3/fOSC1
(
f: Input clock frequency from the prescaler)
When the A/D converter reference voltage
control function is used (VRC = "1"), the time
set in the WAIT register also applies to the
reference voltage setup time. Therefore, design
the peripheral circuit taking the charge time
into consideration. If the reference voltage
(AVREF) cannot be set up within the time set in
the WAIT register, the reference voltage should
be switched on and off by software so that the
setup time is secured.
(5) The capacitors connected to Ch0 and Ch1 of the
touch panel controller (see Figure 5.17.2.1)
affect the pen-down judgement time. They
must be 1000 pF or less.
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