參數(shù)資料
型號(hào)： S1C88409D
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108
封裝： DIE-108
文件頁(yè)數(shù)： 37/250頁(yè)
文件大小： 1877K
代理商： S1C88409D
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S1C88409 TECHNICAL MANUAL
EPSON
121
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer)
ETC0: Timer 0 compare match interrupt enable
register (00FF24HD4)
ETC1: Timer 1 compare match interrupt enable
register (00FF24HD6)
Enables or disables the compare match interrupt
generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
The ETC register is the interrupt enable register
corresponding to the compare match interrupt
factor of each timer.
Interrupt in which the ETC register is set to "1" is
enabled, and the others in which the ETC register
is set to "0" are disabled.
In the 16-bit mode, the setting of the ETC0 is
invalid.
At initial reset, the ETC register is set to "0"
(interrupt is disabled).
FTU0: Timer 0 underflow interrupt factor flag
(00FF28HD3)
FTU1: Timer 1 underflow interrupt factor flag
(00FF28HD5)
Indicates the generation of underflow interrupt
factor.
When "1" is read: Int. factor has generated
When "0" is read: Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FTU is the interrupt factor flag corresponding to
interrupt of each timer, and is set to "1" due to the
counter underflow.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
In the 16-bit mode, the interrupt factor flag FTU0
is not set to "1" and Timer 0 interrupt is not
generated. In this mode, the interrupt factor flag
FTU1 is set to "1" by the underflow of the 16-bit
counter.
At initial reset, the FTU flag is reset to "0".
FTC0: Timer 0 compare match interrupt factor
flag (00FF28HD4)
FTC1: Timer 1 compare match interrupt factor
flag (00FF28HD6)
Indicates the generation of compare match inter-
rupt factor.
When "1" is read: Int. factor has generated
When "0" is read: Int. factor has not generated
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FTC is the interrupt factor flag corresponding to
interrupt of each timer, and is set to "1" due to the
compare match signal.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
In the 16-bit mode, the interrupt factor flag FTC0 is
not set to "1" and Timer 0 interrupt is not gener-
ated. In this mode, the interrupt factor flag FTC1 is
set to "1" by the compare match of the 16-bit
counter.
At initial reset, the FTC flag is reset to "0".
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