參數(shù)資料
型號(hào)： S1C88409D
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.8 MHz, MICROCONTROLLER, UUC108
封裝： DIE-108
文件頁(yè)數(shù)： 66/250頁(yè)
文件大小： 1877K
代理商： S1C88409D
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148
EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
In the 7-bit asynchronous mode, TRXD7 is always
read as "0".
The serial data input from the SIN terminal is
loaded into this buffer after converting into
parallel data as the bit of a high (VDD) level is "1"
and the bit of a low (VSS) level is "0".
At initial reset, the content of the TRXD register is
undefined.
OER: Overrun error flag (00FF41HD4)
Indicates the occurrence of an overrun error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
OER is the error flag that indicates the occurrence
of an overrun error. The flag goes "1" when an
overrun error occurs.
In the asynchronous mode, an overrun error
occurs when the next data is received prior to
writing "1" to RXTRG.
In the clock synchronous slave mode, an overrun
error occurs when the next data is received prior to
reading the received data.
In the clock synchronous master mode, overrun
error does not occur.
The OER flag is reset to "0" by writing "1".
At initial reset and when the RXEN register is "0",
the OER flag is set to "0" (no error).
PER: Parity error flag (00FF41HD5)
Indicates the occurrence of a parity error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
PER is the error flag that indicates the occurrence
of a parity error. The flag goes "1" when a parity
error occurs.
The PER flag is reset to "0" by writing "1".
At initial reset and when the RXEN register is "0",
the PER flag is set to "0" (no error).
FER: Framing error flag (00FF41HD6)
Indicates the occurrence of a framing error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
FER is the error flag that indicates the occurrence
of a framing error. The flag goes "1" when a
framing error occurs.
Framing error occurs when a stop bit is received as
"0".
The FER flag is reset to "0" by writing "1".
At initial reset and when the RXEN register is "0",
the FER flag is set to "0" (no error).
PSI0, PSI1: Interrupt priority register
(00FF21HD4, D5)
Sets the priority level of the serial interface
interrupt.
The PSI register is the interrupt priority register
corresponding to the serial interface interrupt.
Table 5.14.10.3 shows the interrupt priority level
which can be set by this register.
Table 5.14.10.3 Interrupt priority level settings
PSI1
1
0
Interrupt priority level
Level 3
Level 2
Level 1
Level 0
PSI0
1
0
1
0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
At initial reset, the PSI register is set to "0" (level 0).
ESERR, ESRX, ESTX: Interrupt enable register
(00FF24HD0, D1, D2)
Enables or disables the serial interface interrupt
generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
The ESERR, ESRX and ESTX registers are interrupt
enable registers corresponding to the receive error,
receive completion and transmit completion
interrupt factors, respectively.
Interrupt in which the interrupt enable register is
set to "1" is enabled, and the others in which the
register is set to "0" are disabled.
At initial reset, the interrupt enable registers are all
set to "0" (interrupt is disabled).
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