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EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Sampling clock of asynchronous mode
The asynchronous system in this interface gener-
ates a sampling clock on the basis of the output
clock of the 8-bit programmable timer.
However, it is necessary that the 8-bits program-
mable timer has output a clock of 16 times the
baud rate.
(1) At receiving
As shown in Figure 5.14.4.2, duty of the
internal sampling clock is not 50 %. The
sampling clock changes from "1" to "0" with the
second input clock after recognizing a start bit,
and returns to "1" with the eighth clock so that
sampling will be done at the middle of each bit
data received. This sampling waveform is
continuously output until sampling of the stop
bit has completed. Each bit data is sampled at
the rising edge of the sampling clock. When the
stop bit is sampled, the sampling signal is fixed
at "1" until the next start bit is detected.
If the serial input is not "0" at the time of start
bit sampling with the eighth input clock
because the baud rate set in this interface is
different from the transmitter or noise is input
to the SIN terminal, the following data sam-
pling is stopped and the interface shifts into
standby status for the next start bit detection.
(2) At transmission
In transmission, the serial interface generates a
clock for transmission by dividing the output
clock of the 8-bit programmable timer in 1/16
and outputs each bit in synchronization with
the clock.
SIN
8-bit programmable timer
output clock TCLK
Receive sampling clock
Start bit
sampling
Start bit
D0
12
6
×TCLK
10
×TCLK
12
8
16
D0 bit
sampling
Fig. 5.14.4.2 Sampling clock for receiving in asynchronous system
8-bit programmable timer
output clock
Transmission sampling clock
12 3
16
. . .
Fig. 5.14.4.3 Sampling clock for sending in asynchronous system