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EPSON
S1C88409 TECHNICAL MANUAL
CHAPTER 5: PERIPHERAL CIRCUITS AND OPERATION (16-bit Programmable Timer)
PTOUT0: Timer 0 clock output control register
(00FF30HD3)
PTOUT1: Timer 1 clock output control register
(00FF31HD3)
Controls the output of the TOUT signal.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
The PTOUT0 is the output control register for the
TOUT0 signal (Timer 0 output clock). When "1" is
written to this register, the TOUT0 signal is output
from the R40 terminal. When "0" is written, the
terminal goes high (VDD) level. However, the high-
impedance control register HZR40 of the output
port R40 must be set to "0" and the data register
R40D must be set to "1".
The TOUT0 clock cannot be output simultaneously
with the FOUT3 clock.
The PTOUT1 is the output control register for the
TOUT1 signal (Timer 1 output clock). When "1" is
written to this register, the TOUT1 signal is output
from the R41 terminal. When "0" is written, the
terminal goes high (VDD) level. However, the high-
impedance control register HZR41 of the output
port R41 must be set to "0" and the data register
R41D must be set to "1".
The TOUT1 clock cannot be output simultaneously
with the FOUT1 clock.
At initial reset, the PTOUT register is set to "0"
(OFF).
HZR40, HZR41: R4 port high impedance control
register (00FFD4HD0, D1)
Sets the output terminals into a high impedance
state.
When "1" is written: High impedance
When "0" is written: Complementary
Reading: Valid
The HZR40 and HZR41 registers are the high
impedance control registers for the output ports
R40 and R41 used for the clock output.
Fix data of the port used for the TOUT output at
"0".
At initial reset, the HZR register is set to "1" (high
impedance).
R40D, R41D: R4 port output data register
(00FFD9HD0, D1)
They are the data registers for the output ports
R40, R41 used for the clock output.
When "1" is written: Clock output is possible
When "0" is written: LOW (VSS) level is output
Reading: Valid
Fix data of the port used for the TOUT output at
"1".
At initial reset, the data bits are all set to "1".
PTM00, PTM01: Timer 0 interrupt priority
register (00FF20HD0, D1)
PTM10, PTM11: Timer 1 interrupt priority
register (00FF20HD2, D3)
Sets the priority level of the 16-bit programmable
timer interrupt.
The PTM register is the interrupt priority register
corresponding to each timer interrupt.
Table 5.12.7.2 shows the interrupt priority level
which can be set by this register.
Table 5.12.7.2 Interrupt priority level settings
PTM11
PTM01
1
0
Interrupt priority level
Level 3
Level 2
Level 1
Level 0
PTM10
PTM00
1
0
1
0
(IRQ3)
(IRQ2)
(IRQ1)
(None)
At initial reset, the PTM register is set to "0" (level 0).
ETU0: Timer 0 underflow interrupt enable
register (00FF24HD3)
ETU1: Timer 1 underflow interrupt enable
register (00FF24HD5)
Enables or disables the underflow interrupt
generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading: Valid
The ETU register is the interrupt enable register
corresponding to the underflow interrupt factor of
each timer.
Interrupt in which the ETU register is set to "1" is
enabled, and the others in which the ETU register
is set to "0" are disabled.
In the 16-bit mode, the setting of the ETU0 is
invalid.
At initial reset, the ETU register is set to "0"
(interrupt is disabled).